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authorPhilipp Hug <philipp@hug.cx>2024-03-01 10:59:56 +0000
committerron minnich <rminnich@gmail.com>2024-03-04 23:43:46 +0000
commit8e365396d4274b8656fd5c3bd47e9e8953db7e59 (patch)
tree63d37b61ba3ee9db79bbf1e1dbdf80eaa45713e7 /src/arch/riscv/include
parentf3ae0f0cfb56aae82ff877ee74b9c8e83aee9ab9 (diff)
riscv/mb/qemu: fix DRAM probing
Current version of qemu raise an exception when accessing invalid memory. Modify the probing code to temporary redirect the exception handler like on ARM platform. Also move saving of the stack frame out to trap_util.S to have all at the same place for a future rewrite. TEST=boots to ramstage Change-Id: I25860f688c7546714f6fdbce8c8f96da6400813c Signed-off-by: Philipp Hug <philipp@hug.cx> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36486 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/riscv/include')
-rw-r--r--src/arch/riscv/include/arch/exception.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h
index 208cc81e24..9339437019 100644
--- a/src/arch/riscv/include/arch/exception.h
+++ b/src/arch/riscv/include/arch/exception.h
@@ -26,7 +26,7 @@ static inline void exception_init(void)
}
void redirect_trap(void);
-void trap_handler(trapframe *tf);
+void default_trap_handler(trapframe *tf);
void handle_supervisor_call(trapframe *tf);
void handle_misaligned(trapframe *tf);