diff options
| author | Philipp Hug <philipp@hug.cx> | 2019-02-06 06:48:51 +0100 |
|---|---|---|
| committer | ron minnich <rminnich@gmail.com> | 2019-02-13 04:49:14 +0000 |
| commit | b09e5001f3071e82ccf7ec64c9cf9a4768d660b1 (patch) | |
| tree | f1a673efd5da4bcd24886b7c049335f52b8c1c75 /src/arch/riscv/include | |
| parent | 540a66404591ef41e2581df01647e5788ef0c808 (diff) | |
riscv: Add initial support for 32bit boards
* Adding separate targets for 32bit and 64bit qemu
* Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv
* rv32/rv64 is currently configured with ARCH_RISCV_RV32/RV64 and not per stage.
This should probably be changed later.
TEST=Boots to "Payload not loaded." on 32bit qemu using the following commands:
util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf
qemu-system-riscv32 -M virt -m 1024M -nographic -kernel build/coreboot.elf
Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/include')
| -rw-r--r-- | src/arch/riscv/include/arch/smp/spinlock.h | 2 | ||||
| -rw-r--r-- | src/arch/riscv/include/bits.h | 17 | ||||
| -rw-r--r-- | src/arch/riscv/include/mcall.h | 11 |
3 files changed, 23 insertions, 7 deletions
diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h index dc561d30a1..95e60bfefc 100644 --- a/src/arch/riscv/include/arch/smp/spinlock.h +++ b/src/arch/riscv/include/arch/smp/spinlock.h @@ -21,7 +21,7 @@ #define barrier() { asm volatile ("fence" ::: "memory"); } typedef struct { - volatile atomic_t lock; + atomic_t lock; } spinlock_t; static inline void spinlock_lock(spinlock_t *lock) diff --git a/src/arch/riscv/include/bits.h b/src/arch/riscv/include/bits.h index f69c7ec0da..d824f3ec98 100644 --- a/src/arch/riscv/include/bits.h +++ b/src/arch/riscv/include/bits.h @@ -47,10 +47,19 @@ #define STR(x) XSTR(x) #define XSTR(x) #x -# define SLL32 sllw -# define STORE sd -# define LOAD ld -# define LOG_REGBYTES 3 +#if __riscv_xlen == 64 +#define SLL32 sllw +#define STORE sd +#define LOAD ld +#define LWU lwu +#define LOG_REGBYTES 3 +#else +#define SLL32 sll +#define STORE sw +#define LOAD lw +#define LWU lw +#define LOG_REGBYTES 2 +#endif #define REGBYTES (1 << LOG_REGBYTES) diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index cd1ed6dc18..192d2b4564 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -18,7 +18,13 @@ // NOTE: this is the size of hls_t below. A static_assert would be // nice to have. +#if __riscv_xlen == 64 #define HLS_SIZE 88 +#endif + +#if __riscv_xlen == 32 +#define HLS_SIZE 52 +#endif /* We save 37 registers, currently. */ #define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8) @@ -26,6 +32,7 @@ #ifndef __ASSEMBLER__ #include <arch/encoding.h> +#include <arch/smp/atomic.h> #include <stdint.h> typedef struct { @@ -38,8 +45,8 @@ typedef struct { struct blocker { void *arg; void (*fn)(void *arg); - uint32_t sync_a; - uint32_t sync_b; + atomic_t sync_a; + atomic_t sync_b; }; typedef struct { |