summaryrefslogtreecommitdiff
path: root/src/arch/riscv/include
diff options
context:
space:
mode:
authorSubrata Banik <subratabanik@google.com>2022-01-03 18:49:35 +0000
committerFelix Held <felix-coreboot@felixheld.de>2022-01-21 16:02:34 +0000
commit6fb126773f538ea4467b1abfde6cb8c6fc3cc9bb (patch)
treec99ad2d7009db445105a60b672849c42eba21fa7 /src/arch/riscv/include
parentcef6770a0bf0cbe06a044ada7a28812cbd22afe8 (diff)
soc/intel/ehl: Replace dt `HeciEnabled` by `HECI1 disable` config
The only option to make HECI1 function disable on Elkhart Lake SoC platform is using SBI under SMM mode. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/arch/riscv/include')
0 files changed, 0 insertions, 0 deletions