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authorXiang Wang <wxjstz@126.com>2018-08-15 16:27:05 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-11-05 09:04:01 +0000
commit22e0c560bb565642d52e4e0f8bab000c8d06f0b8 (patch)
treea960e9bc01d3d4d9ddb65ba828b64d39a64baade /src/arch/riscv/include
parent26f725efc235b282e20aa678f8e683a014920b71 (diff)
riscv: add support for supervisor binary interface (SBI)
SBI is runtime service for OS. For an introduction, please refer to https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/include')
-rw-r--r--src/arch/riscv/include/sbi.h37
-rw-r--r--src/arch/riscv/include/vm.h8
2 files changed, 45 insertions, 0 deletions
diff --git a/src/arch/riscv/include/sbi.h b/src/arch/riscv/include/sbi.h
new file mode 100644
index 0000000000..e9301f630c
--- /dev/null
+++ b/src/arch/riscv/include/sbi.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 HardenedLinux
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef RISCV_SBI_H
+#define RISCV_SBI_H
+
+#define SBI_SET_TIMER 0
+#define SBI_CONSOLE_PUTCHAR 1
+#define SBI_CONSOLE_GETCHAR 2
+#define SBI_CLEAR_IPI 3
+#define SBI_SEND_IPI 4
+#define SBI_REMOTE_FENCE_I 5
+#define SBI_REMOTE_SFENCE_VMA 6
+#define SBI_REMOTE_SFENCE_VMA_ASID 7
+#define SBI_SHUTDOWN 8
+
+#define IPI_SOFT 1
+#define IPI_FENCE_I 2
+#define IPI_SFENCE_VMA 4
+#define IPI_SFENCE_VMA_ASID 8
+#define IPI_SHUTDOWN 16
+
+void handle_sbi(trapframe *tf);
+
+#endif /* RISCV_SBI_H */
diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h
index 749c9c86bf..9f6236ea75 100644
--- a/src/arch/riscv/include/vm.h
+++ b/src/arch/riscv/include/vm.h
@@ -102,6 +102,14 @@ DEFINE_MPRV_WRITE(mprv_write_u64, uint64_t, sd)
DEFINE_MPRV_WRITE(mprv_write_long, long, sd)
DEFINE_MPRV_WRITE(mprv_write_ulong, unsigned long, sd)
+#if __riscv_xlen == 32
+ DEFINE_MPRV_READ(mprv_read_uintptr_t, uintptr_t, lw)
+ DEFINE_MPRV_READ(mprv_write_uintptr_t, uintptr_t, sw)
+#elif __riscv_xlen == 64
+ DEFINE_MPRV_READ(mprv_read_uintptr_t, uintptr_t, ld)
+ DEFINE_MPRV_READ(mprv_write_uintptr_t, uintptr_t, sd)
+#endif
+
#undef DEFINE_MPRV_READ_FLAGS
#undef DEFINE_MPRV_READ
#undef DEFINE_MPRV_READ_MXR