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authorElyes HAOUAS <ehaouas@noos.fr>2016-09-03 08:28:48 +0200
committerMartin Roth <martinroth@google.com>2016-09-12 20:05:30 +0200
commit6b72787d270077969869e9b17b88a63539f172b4 (patch)
treef203c91e18b7a1320783f4b1e478c335d6696f3e /src/arch/riscv/include
parentc7702536ed7b9d80058e2d41c396828c3a1ac20b (diff)
src/arch: Improve code formatting
Change-Id: Ic1ca6c2e1cd06800d7eb2d00ac0b328987d022ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16434 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
Diffstat (limited to 'src/arch/riscv/include')
-rw-r--r--src/arch/riscv/include/arch/cpu.h6
-rw-r--r--src/arch/riscv/include/arch/hlt.h2
2 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h
index 7e8ec63bae..bc7b1962a3 100644
--- a/src/arch/riscv/include/arch/cpu.h
+++ b/src/arch/riscv/include/arch/cpu.h
@@ -37,9 +37,9 @@ struct cpu_info {
};
struct cpuinfo_riscv {
- uint8_t riscv; /* CPU family */
- uint8_t riscv_vendor; /* CPU vendor */
- uint8_t riscv_model;
+ uint8_t riscv; /* CPU family */
+ uint8_t riscv_vendor; /* CPU vendor */
+ uint8_t riscv_model;
};
#endif
diff --git a/src/arch/riscv/include/arch/hlt.h b/src/arch/riscv/include/arch/hlt.h
index de2f25c5af..da0277821b 100644
--- a/src/arch/riscv/include/arch/hlt.h
+++ b/src/arch/riscv/include/arch/hlt.h
@@ -13,5 +13,5 @@
static inline __attribute__((always_inline)) void hlt(void)
{
- while(1);
+ while (1);
}