diff options
| author | Xiang Wang <wxjstz@126.com> | 2018-08-15 16:27:05 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-05 09:04:01 +0000 |
| commit | 22e0c560bb565642d52e4e0f8bab000c8d06f0b8 (patch) | |
| tree | a960e9bc01d3d4d9ddb65ba828b64d39a64baade /src/arch/riscv/include/vm.h | |
| parent | 26f725efc235b282e20aa678f8e683a014920b71 (diff) | |
riscv: add support for supervisor binary interface (SBI)
SBI is runtime service for OS. For an introduction, please refer to
https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md
Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/include/vm.h')
| -rw-r--r-- | src/arch/riscv/include/vm.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index 749c9c86bf..9f6236ea75 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -102,6 +102,14 @@ DEFINE_MPRV_WRITE(mprv_write_u64, uint64_t, sd) DEFINE_MPRV_WRITE(mprv_write_long, long, sd) DEFINE_MPRV_WRITE(mprv_write_ulong, unsigned long, sd) +#if __riscv_xlen == 32 + DEFINE_MPRV_READ(mprv_read_uintptr_t, uintptr_t, lw) + DEFINE_MPRV_READ(mprv_write_uintptr_t, uintptr_t, sw) +#elif __riscv_xlen == 64 + DEFINE_MPRV_READ(mprv_read_uintptr_t, uintptr_t, ld) + DEFINE_MPRV_READ(mprv_write_uintptr_t, uintptr_t, sd) +#endif + #undef DEFINE_MPRV_READ_FLAGS #undef DEFINE_MPRV_READ #undef DEFINE_MPRV_READ_MXR |