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| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-22 13:15:12 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-26 10:20:35 +0000 |
| commit | ca2f68abedcc2065574a03a4525b1c3cab7280ba (patch) | |
| tree | d471c91bb08df1a5ecfc624855f61e4b0f258679 /src/arch/riscv/fp_asm.S | |
| parent | 5fd50b6b198d7e086945ca0255ccc0757b31f748 (diff) | |
nb/intel/sandybridge: Correct TC_DTP handling
It is only for Ivy Bridge, and needs to be set on certain circumstances.
Change-Id: I4093adef44fae787c96fec4b4b8c7c867786d219
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch/riscv/fp_asm.S')
0 files changed, 0 insertions, 0 deletions