diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-15 13:26:21 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:11:37 +0000 |
| commit | c674223fd419709da2907e8c839131e3250daa25 (patch) | |
| tree | 51739621a386c74533681d0a2a1cf987157175db /src/arch/riscv/bootblock.S | |
| parent | 4c76d25717048c71533c67cec21085dfc27538f9 (diff) | |
nb/intel/sandybridge: Remove spurious writes to IOSAV BW mask
The byte-wise error mask only needs to be set for certain corner cases
in read MPR training. Thus, minimize writes to this register.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I0bb8d99ad60c4964f896d303878e5982ae1dcdbe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/arch/riscv/bootblock.S')
0 files changed, 0 insertions, 0 deletions