diff options
| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-02-16 13:36:47 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-20 20:46:12 +0000 |
| commit | 042a8336f3eb7c7ed4358a100fae23967346e7a2 (patch) | |
| tree | 50751f64e4352cc518b02b6ce9a9c1a388c23f58 /src/arch/riscv/bootblock.S | |
| parent | b26759d703b636d1462d31cfa38fd3b3d8c90bfe (diff) | |
arch/riscv: Pass the bootrom-provided FDT to the payload
The RISC-V boot protocol foresees that at every stage boundary (bootrom
to boot loader, boot loader -> OS), register a0 contains the Hart ID and
a1 contains the physical address of the Flattened Device Tree that the
stage shall use.
As a first step, pass the bootrom-provided FDT to the payload,
unmodified.
Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/bootblock.S')
| -rw-r--r-- | src/arch/riscv/bootblock.S | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 43bca907bb..0b5a2b2961 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -25,7 +25,14 @@ .globl _start _start: - + # The boot ROM may pass the following arguments to coreboot: + # a0: the value of mhartid + # a1: a pointer to the flattened devicetree + # + # Preserve only the FDT pointer. We can query mhartid ourselves at any + # time. + # + csrw mscratch, a1 # N.B. This only works on low 4G of the address space # and the stack must be page-aligned. |