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| author | Subrata Banik <subrata.banik@intel.com> | 2015-08-22 11:10:22 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-25 18:56:52 +0000 |
| commit | e5e9439715c738f8e4217aa5c03d90b3b9d4e9db (patch) | |
| tree | cb92dc61c89082852c06090b2188571c816f1272 /src/arch/riscv/boot.c | |
| parent | 51ee7ce3eacb4a58d9a806211c1739c3ff1fb8ee (diff) | |
google/cyan: Support reading Memory strap GPIOs to select SPD
Cherry-pick from Chromium commit 8f63720.
SoC GPIO to read Memory strap not getting configured
correctly causing incorrect RAMID read during ROMSTAGE
TEST=Build and boot the platform with differnt Memory type and
read RAMID correctly inside spd.c
RAMID = 0 => 4GB Samsung Memory
RAMID = 1 => 4GB Hynix Memory
RAMID = 2 => 2GB Samsung Memory
RAMID = 3 => 2GB Hynix Memory
Original-Change-Id: Ide9d4b5f73565cddd74cedf7afe4b7d168dde74c
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: If2ba9ec5be111b9c30360ffde41a2c644a69ecae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/arch/riscv/boot.c')
0 files changed, 0 insertions, 0 deletions