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| author | Philipp Hug <philipp@hug.cx> | 2019-02-06 06:48:51 +0100 |
|---|---|---|
| committer | ron minnich <rminnich@gmail.com> | 2019-02-13 04:49:14 +0000 |
| commit | b09e5001f3071e82ccf7ec64c9cf9a4768d660b1 (patch) | |
| tree | f1a673efd5da4bcd24886b7c049335f52b8c1c75 /src/arch/riscv/Makefile.inc | |
| parent | 540a66404591ef41e2581df01647e5788ef0c808 (diff) | |
riscv: Add initial support for 32bit boards
* Adding separate targets for 32bit and 64bit qemu
* Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv
* rv32/rv64 is currently configured with ARCH_RISCV_RV32/RV64 and not per stage.
This should probably be changed later.
TEST=Boots to "Payload not loaded." on 32bit qemu using the following commands:
util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf
qemu-system-riscv32 -M virt -m 1024M -nographic -kernel build/coreboot.elf
Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/Makefile.inc')
| -rw-r--r-- | src/arch/riscv/Makefile.inc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 9d91f0cefe..d5f62954eb 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -86,6 +86,10 @@ $(objcbfs)/bootblock.debug: $$(bootblock-objs) bootblock-c-ccopts += $(riscv_flags) bootblock-S-ccopts += $(riscv_asm_flags) +ifeq ($(CONFIG_ARCH_RISCV_RV32),y) +LDFLAGS_bootblock += -m elf32lriscv +endif #CONFIG_ARCH_RISCV_RV32 + endif #CONFIG_ARCH_BOOTBLOCK_RISCV ################################################################################ @@ -116,6 +120,10 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) romstage-c-ccopts += $(riscv_flags) romstage-S-ccopts += $(riscv_asm_flags) +ifeq ($(CONFIG_ARCH_RISCV_RV32),y) +LDFLAGS_romstage += -m elf32lriscv +endif #CONFIG_ARCH_RISCV_RV32 + endif #CONFIG_ARCH_ROMSTAGE_RISCV ################################################################################ @@ -161,5 +169,9 @@ $(objcbfs)/ramstage.debug: $$(ramstage-objs) ramstage-c-ccopts += $(riscv_flags) ramstage-S-ccopts += $(riscv_asm_flags) +ifeq ($(CONFIG_ARCH_RISCV_RV32),y) +LDFLAGS_ramstage += -m elf32lriscv +endif #CONFIG_ARCH_RISCV_RV32 + endif #CONFIG_ARCH_RAMSTAGE_RISCV endif #CONFIG_ARCH_RISCV |