diff options
| author | Xiang Wang <wxjstz@126.com> | 2018-08-09 16:20:35 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-10 15:03:58 +0000 |
| commit | cda59b56ba1af83a64579901a5395c1b3c1bf519 (patch) | |
| tree | 1ea1d63305663f76623b8db878e33f72b4867f82 /src/arch/riscv/Makefile.inc | |
| parent | aa5f821ee3313b869784eec25fab5da265225738 (diff) | |
riscv: update misaligned memory access exception handling
Support for more situations: floating point, compressed instructions,
etc. Add support for redirect exception to S-Mode.
Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'src/arch/riscv/Makefile.inc')
| -rw-r--r-- | src/arch/riscv/Makefile.inc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index ae327f2f16..f4b69bb95e 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -43,6 +43,8 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y) bootblock-y = bootblock.S bootblock-y += trap_util.S bootblock-y += trap_handler.c +bootblock-y += fp_asm.S +bootblock-y += misaligned.c bootblock-y += mcall.c bootblock-y += virtual_memory.c bootblock-y += boot.c @@ -101,6 +103,8 @@ ramstage-y += ramstage.S ramstage-y += mcall.c ramstage-y += trap_util.S ramstage-y += trap_handler.c +ramstage-y += fp_asm.S +ramstage-y += misaligned.c ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c |