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| author | Ronald G. Minnich <rminnich@gmail.com> | 2016-11-06 20:54:20 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2016-11-12 19:23:22 +0100 |
| commit | 574df1ba670aaac265ba44b2c94e831dfff9f96d (patch) | |
| tree | 229c0ab937fbee26b1c8c8c79b5c105afae06204 /src/arch/riscv/Kconfig | |
| parent | 04c94ded3a1b4143c3186321a95c547af5377d99 (diff) | |
riscv: start to use the configstring functions
These functions will allow us to remove hardcodes,
as long as we can verify the qemu and lowrisc targets
implement the configstring correctly. Hence, for the
most part, we'll start with mainboard changes first.
Define a new config variable, CONFIG_RISCV_CONFIGSTRING,
which has a default value that works on all existing
systems but which can be changed
as needed for a new SOC or mainboard.
Change-Id: I7dd3f553d3e61f1c49752fb04402b134fdfdf979
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17256
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'src/arch/riscv/Kconfig')
| -rw-r--r-- | src/arch/riscv/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index a30cb7091b..f05a98b106 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -19,3 +19,8 @@ config ARCH_ROMSTAGE_RISCV config ARCH_RAMSTAGE_RISCV bool default n + +config RISCV_CONFIGSTRING + hex "Location of pointer to RISCV config string" + default 0x100c + depends on ARCH_RISCV |