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authorLean Sheng Tan <sheng.tan@9elements.com>2023-03-15 15:32:01 +0100
committerLean Sheng Tan <sheng.tan@9elements.com>2023-04-15 14:36:29 +0000
commitce68d68e00bb4801b34efdd15eb786653a961d38 (patch)
treed9d8751eebc7e96076678aa04dd9a12d9a5552d2 /src/arch/ppc64
parentab496bf1770b4b2a1b0f6a99e14e736c43190b44 (diff)
soc/intel/alderlake: Enable early caching of RAMTOP region
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). TEST=Able to build and boot Starlab ADL laptop to OS. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73736 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Diffstat (limited to 'src/arch/ppc64')
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