This patch unifies the use of config options in v2 to all start with CONFIG_

It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 19 insertions, 19 deletions

diff --git a/src/arch/ppc/init/crt0.S.lb b/src/arch/ppc/init/crt0.S.lb
index 738d4b4a67..bbccc59213 100644
--- a/src/arch/ppc/init/crt0.S.lb
+++ b/src/arch/ppc/init/crt0.S.lb
@@ -30,8 +30,8 @@ system_reset:
 	 */
 %%PROCESSOR_INIT%%
 
-#if USE_DCACHE_RAM == 1
-#define DCACHE_RAM_END	(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - 1)
+#if CONFIG_USE_DCACHE_RAM == 1
+#define DCACHE_RAM_END	(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 1)
 	/*
 	 * Initialize data cache blocks 
 	 * (assumes cache block size of 32 bytes)
@@ -39,9 +39,9 @@ system_reset:
 	 * NOTE: This may need to be moved to FAMILY_INIT if
 	 *       dcbz is not supported on all CPU's
 	 */
-	lis     r1, DCACHE_RAM_BASE@h
-	ori     r1, r1, DCACHE_RAM_BASE@l
-	li      r3, (DCACHE_RAM_SIZE / 32)
+	lis     r1, CONFIG_DCACHE_RAM_BASE@h
+	ori     r1, r1, CONFIG_DCACHE_RAM_BASE@l
+	li      r3, (CONFIG_DCACHE_RAM_SIZE / 32)
 	mtctr   r3
 0:      dcbz    r0, r1
 	addi    r1, r1, 32
@@ -53,8 +53,8 @@ system_reset:
 	 * it 16-byte aligned to cover both cases. Also we have to ensure that
 	 * the first word is located within the cache.
 	 */
-	lis     r1, (DCACHE_RAM_BASE+DCACHE_RAM_SIZE)@h
-	ori     r1, r1, (DCACHE_RAM_BASE+DCACHE_RAM_SIZE)@l
+	lis     r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@h
+	ori     r1, r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@l
 	lis	r0, 0
 	stwu	r0, -4(r1)
 	stwu	r0, -4(r1)
@@ -65,8 +65,8 @@ system_reset:
 	/*
 	 * Clear stack
 	 */
-	lis	r4, DCACHE_RAM_BASE@h
-	ori	r4, r4, DCACHE_RAM_BASE@l
+	lis	r4, CONFIG_DCACHE_RAM_BASE@h
+	ori	r4, r4, CONFIG_DCACHE_RAM_BASE@l
 	lis	r7, DCACHE_RAM_END@h
 	ori	r7, r7, DCACHE_RAM_END@l
 	lis	r5, 0
@@ -110,7 +110,7 @@ system_reset:
 	 * Complete rest of initialization in C (ppc_main)
 	 */
 	rfi
-#endif /* USE_DCACHE_RAM */
+#endif /* CONFIG_USE_DCACHE_RAM */
 
 	/*
 	 * Stop here if something goes wrong
diff --git a/src/arch/ppc/init/ldscript.lb b/src/arch/ppc/init/ldscript.lb
index a81d9b9bb8..453c99c13b 100644
--- a/src/arch/ppc/init/ldscript.lb
+++ b/src/arch/ppc/init/ldscript.lb
@@ -1,14 +1,14 @@
 /*
  *	Memory map:
  *
- *	_ROMBASE		: start of ROM
- *	_RESET			: reset vector (may be at top of ROM)
+ *	CONFIG_ROMBASE		: start of ROM
+ *	CONFIG_RESET			: reset vector (may be at top of ROM)
  *	_EXCEPTIONS_VECTORS	: exception table
  *
- *	_ROMSTART 		: coreboot text 
+ *	CONFIG_ROMSTART 		: coreboot text 
  *				: payload text
  *
- *	_RAMBASE		: address to copy payload
+ *	CONFIG_RAMBASE		: address to copy payload
  */
 
 /*
@@ -32,13 +32,13 @@ SECTIONS
 	/* 
 	 * Absolute location of base of ROM 
 	 */
-	. = _ROMBASE;
+	. = CONFIG_ROMBASE;
 
 	/*
 	 * Absolute location of reset vector. This may actually be at the
 	 * the top of ROM.
 	 */
-	. = _RESET;
+	. = CONFIG_RESET;
 	.reset . : {
 		*(.rom.reset);
 		. = ALIGN(16);
@@ -47,7 +47,7 @@ SECTIONS
 	/*
 	 * Absolute location of exception vector table.
 	 */
-	. = _EXCEPTION_VECTORS;
+	. = CONFIG_EXCEPTION_VECTORS;
 	.exception_vectors . : {
 		*(.rom.exception_vectors);
 		. = ALIGN(16);
@@ -56,7 +56,7 @@ SECTIONS
 	/*
 	 * Absolute location of coreboot initialization code in ROM.
 	 */
-	. = _ROMSTART;
+	. = CONFIG_ROMSTART;
 	.rom . : {
 		_rom = .;
 		*(.rom.text);
@@ -94,7 +94,7 @@ SECTIONS
 	/*
 	 * Absolute location of where coreboot will be relocated in RAM.
 	 */
-	_iseg = _RAMBASE;
+	_iseg = CONFIG_RAMBASE;
 	_eiseg = _iseg + SIZEOF(.ram);
 	_liseg = _ram;
 	_eliseg = _eram;