Moved from freebios

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

10 files changed, 798 insertions, 0 deletions

diff --git a/src/arch/ppc/include/arch/boot/boot.h b/src/arch/ppc/include/arch/boot/boot.h
new file mode 100644
index 0000000000..b68455b557
--- /dev/null
+++ b/src/arch/ppc/include/arch/boot/boot.h
@@ -0,0 +1,8 @@
+#ifndef ASM_I386_BOOT_H
+#define ASM_I386_BOOT_H
+
+#define ELF_CLASS	ELFCLASS32
+#define ELF_DATA	ELFDATA2MSB
+#define ELF_ARCH	EM_PPC
+
+#endif /* ASM_I386_BOOT_H */
diff --git a/src/arch/ppc/include/arch/io.h b/src/arch/ppc/include/arch/io.h
new file mode 100644
index 0000000000..f51f14089e
--- /dev/null
+++ b/src/arch/ppc/include/arch/io.h
@@ -0,0 +1,192 @@
+/*
+ * BK Id: SCCS/s.io.h 1.14 10/16/01 15:58:42 trini
+ */
+#ifndef _PPC_IO_H
+#define _PPC_IO_H
+#include <types.h>
+
+#define SIO_CONFIG_RA	0x398
+#define SIO_CONFIG_RD	0x399
+
+#define SLOW_DOWN_IO
+
+#define PMAC_ISA_MEM_BASE 	0
+#define PMAC_PCI_DRAM_OFFSET 	0
+#define CHRP_ISA_IO_BASE 	0xf8000000
+#define CHRP_ISA_MEM_BASE 	0xf7000000
+#define CHRP_PCI_DRAM_OFFSET 	0
+#define PREP_ISA_IO_BASE 	0x80000000
+#define PREP_ISA_MEM_BASE 	0xc0000000
+#define PREP_PCI_DRAM_OFFSET 	0x80000000
+
+#define _IO_BASE		0xfe000000
+
+#define readb(addr) in_8((volatile u8 *)(addr))
+#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
+#define readw(addr) in_le16((volatile u16 *)(addr))
+#define readl(addr) in_le32((volatile u32 *)(addr))
+#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
+#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
+
+
+#define __raw_readb(addr)	(*(volatile unsigned char *)(addr))
+#define __raw_readw(addr)	(*(volatile unsigned short *)(addr))
+#define __raw_readl(addr)	(*(volatile unsigned int *)(addr))
+#define __raw_writeb(v, addr)	(*(volatile unsigned char *)(addr) = (v))
+#define __raw_writew(v, addr)	(*(volatile unsigned short *)(addr) = (v))
+#define __raw_writel(v, addr)	(*(volatile unsigned int *)(addr) = (v))
+
+/*
+ * The insw/outsw/insl/outsl macros don't do byte-swapping.
+ * They are only used in practice for transferring buffers which
+ * are arrays of bytes, and byte-swapping is not appropriate in
+ * that case.  - paulus
+ */
+#define insb(port, buf, ns)	_insb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define outsb(port, buf, ns)	_outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define insw(port, buf, ns)	_insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw(port, buf, ns)	_outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl(port, buf, nl)	_insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl(port, buf, nl)	_outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define inb(port)		in_8((u8 *)((port)+_IO_BASE))
+#define outb(val, port)		out_8((u8 *)((port)+_IO_BASE), (val))
+#define inw(port)		in_le16((u16 *)((port)+_IO_BASE))
+#define outw(val, port)		out_le16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port)		in_le32((u32 *)((port)+_IO_BASE))
+#define outl(val, port)		out_le32((u32 *)((port)+_IO_BASE), (val))
+
+#define inb_p(port)		inb((port))
+#define outb_p(val, port)	outb((val), (port))
+#define inw_p(port)		inw((port))
+#define outw_p(val, port)	outw((val), (port))
+#define inl_p(port)		inl((port))
+#define outl_p(val, port)	outl((val), (port))
+
+extern void _insb(volatile u8 *port, void *buf, int ns);
+extern void _outsb(volatile u8 *port, const void *buf, int ns);
+extern void _insw(volatile u16 *port, void *buf, int ns);
+extern void _outsw(volatile u16 *port, const void *buf, int ns);
+extern void _insl(volatile u32 *port, void *buf, int nl);
+extern void _outsl(volatile u32 *port, const void *buf, int nl);
+extern void _insw_ns(volatile u16 *port, void *buf, int ns);
+extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
+extern void _insl_ns(volatile u32 *port, void *buf, int nl);
+extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
+
+/*
+ * The *_ns versions below don't do byte-swapping.
+ * Neither do the standard versions now, these are just here
+ * for older code.
+ */
+#define insw_ns(port, buf, ns)	_insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw_ns(port, buf, ns)	_outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl_ns(port, buf, nl)	_insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl_ns(port, buf, nl)	_outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+
+#define IO_SPACE_LIMIT ~0
+
+#define memset_io(a,b,c)       memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c)	memcpy((void *)(a),(b),(c))
+
+/*
+ * Enforce In-order Execution of I/O:
+ * Acts as a barrier to ensure all previous I/O accesses have
+ * completed before any further ones are issued.
+ */
+extern inline void eieio(void)
+{
+	__asm__ __volatile__ ("eieio" : : : "memory");
+}
+
+/* Enforce in-order execution of data I/O. 
+ * No distinction between read/write on PPC; use eieio for all three.
+ */
+#define iobarrier_rw() eieio()
+#define iobarrier_r()  eieio()
+#define iobarrier_w()  eieio()
+
+/*
+ * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ */
+extern inline int in_8(volatile unsigned char *addr)
+{
+	int ret;
+
+	__asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+	return ret;
+}
+
+extern inline void out_8(volatile unsigned char *addr, int val)
+{
+	__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+
+extern inline int in_le16(volatile unsigned short *addr)
+{
+	int ret;
+
+	__asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) :
+			      "r" (addr), "m" (*addr));
+	return ret;
+}
+
+extern inline int in_be16(volatile unsigned short *addr)
+{
+	int ret;
+
+	__asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+	return ret;
+}
+
+extern inline void out_le16(volatile unsigned short *addr, int val)
+{
+	__asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
+			      "r" (val), "r" (addr));
+}
+
+extern inline void out_be16(volatile unsigned short *addr, int val)
+{
+	__asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+
+extern inline unsigned in_le32(volatile unsigned *addr)
+{
+	unsigned ret;
+
+	__asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
+			     "r" (addr), "m" (*addr));
+	return ret;
+}
+
+extern inline unsigned in_be32(volatile unsigned *addr)
+{
+	unsigned ret;
+
+	__asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+	return ret;
+}
+
+extern inline void out_le32(volatile unsigned *addr, int val)
+{
+	__asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
+			     "r" (val), "r" (addr));
+}
+
+extern inline void out_be32(volatile unsigned *addr, int val)
+{
+	__asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+
+extern inline void _insw_ns(volatile u16 *port, void *buf, int ns)
+{
+	u16 *   b = (u16 *)buf;    
+
+	while (ns > 0) {    
+		*b++ = readw(port);
+		ns--;
+	}
+}
+#endif
diff --git a/src/arch/ppc/include/arch/pirq_routing.h b/src/arch/ppc/include/arch/pirq_routing.h
new file mode 100644
index 0000000000..dad8531eb5
--- /dev/null
+++ b/src/arch/ppc/include/arch/pirq_routing.h
@@ -0,0 +1,54 @@
+#ifndef ARCH_PIRQ_ROUTING_H
+#define ARCH_PIRQ_ROUTING_H
+
+#include <types.h>
+
+#define PIRQ_SIGNATURE	(('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
+#define PIRQ_VERSION 0x0100
+
+struct irq_info {
+	u8 bus, devfn;			/* Bus, device and function */
+	struct {
+		u8 link;		/* IRQ line ID, chipset dependent, 0=not routed */
+		u16 bitmap;		/* Available IRQs */
+	} __attribute__((packed)) irq[4];
+	u8 slot;			/* Slot number, 0=onboard */
+	u8 rfu;
+} __attribute__((packed));
+
+#if defined(IRQ_SLOT_COUNT)
+#define IRQ_SLOTS_COUNT IRQ_SLOT_COUNT
+#elif (__GNUC__ < 3)
+#define IRQ_SLOTS_COUNT 1
+#else
+#define IRQ_SLOTS_COUNT
+#endif
+
+struct irq_routing_table {
+	u32 signature;			/* PIRQ_SIGNATURE should be here */
+	u16 version;			/* PIRQ_VERSION */
+	u16 size;			/* Table size in bytes */
+	u8 rtr_bus, rtr_devfn;		/* Where the interrupt router lies */
+	u16 exclusive_irqs;		/* IRQs devoted exclusively to PCI usage */
+	u16 rtr_vendor, rtr_device;	/* Vendor and device ID of interrupt router */
+	u32 miniport_data;		/* Crap */
+	u8 rfu[11];
+	u8 checksum;			/* Modulo 256 checksum must give zero */
+	struct irq_info slots[IRQ_SLOTS_COUNT];
+} __attribute__((packed));
+
+extern const struct irq_routing_table intel_irq_routing_table;
+
+#if defined(DEBUG) && defined(HAVE_PIRQ_TABLE)
+void check_pirq_routing_table(void);
+#else
+#define check_pirq_routing_table() do {} while(0)
+#endif
+
+#if defined(HAVE_PIRQ_TABLE)
+unsigned long copy_pirq_routing_table(unsigned long start);
+#else
+#define copy_pirq_routing_table(start) (start)
+#endif
+
+#endif /* ARCH_PIRQ_ROUTING_H */
diff --git a/src/arch/ppc/include/bitops.h b/src/arch/ppc/include/bitops.h
new file mode 100644
index 0000000000..23cfa66077
--- /dev/null
+++ b/src/arch/ppc/include/bitops.h
@@ -0,0 +1,22 @@
+#ifndef I386_BITOPS_H
+#define I386_BITOPS_H
+
+/**
+ * log2 - Find the truncated log base 2 of x
+ */
+
+static inline unsigned long log2(unsigned long x)
+{
+	unsigned long r = 0;
+	/*
+	__asm__(
+		"bsrl %1, %0\n\t"
+		"jnz 1f\n\t"
+		"movl $-1, %0\n\t"
+		"1:\n\t"
+		: "=r" (r) : "r" (x));
+		 */
+	return r;
+		
+}
+#endif /* I386_BITOPS_H */
diff --git a/src/arch/ppc/include/ppc.h b/src/arch/ppc/include/ppc.h
new file mode 100644
index 0000000000..fe4aa1654b
--- /dev/null
+++ b/src/arch/ppc/include/ppc.h
@@ -0,0 +1,21 @@
+/* $Id$ */
+/* Copyright 2000  AG Electronics Ltd. */
+/* This code is distributed without warranty under the GPL v2 (see COPYING) */
+
+#ifndef _PPC_H
+#define _PPC_H
+
+#define BIG_ENDIAN
+#define RODATA __attribute__ ((__section__ (".rodata"))) 
+
+/* Do CPU specific setup, with optional icache */
+void ppc_setup_cpu(int icache);
+
+void ppc_enable_dcache(void);
+void ppc_disable_dcache(void);
+void ppc_enable_mmu(void);
+
+/* Describe which sort of ppc CPU I am */
+void ppc_identify(void);
+
+#endif
diff --git a/src/arch/ppc/include/ppc_asm.tmpl b/src/arch/ppc/include/ppc_asm.tmpl
new file mode 100644
index 0000000000..da1f7f7782
--- /dev/null
+++ b/src/arch/ppc/include/ppc_asm.tmpl
@@ -0,0 +1,293 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains all the macros and symbols which define
+ * a PowerPC assembly language environment.
+ */
+#ifndef	__PPC_ASM_TMPL__
+#define __PPC_ASM_TMPL__
+
+/***************************************************************************
+ *
+ * These definitions simplify the ugly declarations necessary for GOT
+ * definitions.
+ *
+ * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
+ *
+ * Uses r14 to access the GOT
+ */
+
+#define START_GOT			\
+	.section	".got2","aw";	\
+.LCTOC1 = .+32768
+
+#define END_GOT				\
+	.text
+
+#define GET_GOT				\
+	bl	1f		;	\
+	.text	2		;	\
+0:	.long	.LCTOC1-1f	;	\
+	.text			;	\
+1:	mflr	r14		;	\
+	lwz	r0,0b-1b(r14)	;	\
+	add	r14,r0,r14	;
+
+#define GOT_ENTRY(NAME)		.L_ ## NAME = . - .LCTOC1 ; .long NAME
+
+#define GOT(NAME)		.L_ ## NAME (r14)
+
+
+/***************************************************************************
+ * Register names
+ */
+#define	r0	0
+#define	r1	1
+#define	r2	2
+#define	r3	3
+#define	r4	4
+#define	r5	5
+#define	r6	6
+#define	r7	7
+#define	r8	8
+#define	r9	9
+#define	r10	10
+#define	r11	11
+#define	r12	12
+#define	r13	13
+#define	r14	14
+#define	r15	15
+#define	r16	16
+#define	r17	17
+#define	r18	18
+#define	r19	19
+#define	r20	20
+#define	r21	21
+#define	r22	22
+#define	r23	23
+#define	r24	24
+#define	r25	25
+#define	r26	26
+#define	r27	27
+#define	r28	28
+#define	r29	29
+#define	r30	30
+#define	r31	31
+
+/*
+ * FP register names
+ */
+#define	fr0	0
+#define	fr1	1
+#define	fr2	2
+#define	fr3	3
+#define	fr4	4
+#define	fr5	5
+#define	fr6	6
+#define	fr7	7
+#define	fr8	8
+#define	fr9	9
+#define	fr10	10
+#define	fr11	11
+#define	fr12	12
+#define	fr13	13
+#define	fr14	14
+#define	fr15	15
+#define	fr16	16
+#define	fr17	17
+#define	fr18	18
+#define	fr19	19
+#define	fr20	20
+#define	fr21	21
+#define	fr22	22
+#define	fr23	23
+#define	fr24	24
+#define	fr25	25
+#define	fr26	26
+#define	fr27	27
+#define	fr28	28
+#define	fr29	29
+#define	fr30	30
+#define	fr31	31
+
+/* Some special registers */
+
+#define	TBRU	269	/* Time base Upper/Lower (Reading) */
+#define	TBRL	268
+#define TBWU	284	/* Time base Upper/Lower (Writing) */
+#define TBWL	285
+#define	XER	1
+#define LR	8
+#define CTR	9
+#define HID0	1008	/* Hardware Implementation */
+#define PVR	287	/* Processor Version */
+#define SDR1	25	/* MMU hash base register */
+#define DAR	19	/* Data Address Register */
+#define SPR0	272	/* Supervisor Private Registers */
+#define SPRG0   272
+#define SPR1	273
+#define SPRG1   273
+#define SPR2	274
+#define SPRG2   274
+#define SPR3	275
+#define SPRG3   275
+#define DSISR	18
+#define SRR0	26	/* Saved Registers (exception) */
+#define SRR1	27
+#define DEC	22	/* Decrementer */
+#define EAR	282	/* External Address Register */
+#define ICR	148	/* Interrupt Cause Register (37-44) */
+#define DER	149
+#define COUNTA	150	/* Breakpoint Counter	    (37-44) */
+#define COUNTB	151	/* Breakpoint Counter	    (37-44) */
+#define LCTRL1	156	/* Load/Store Support	    (37-40) */
+#define LCTRL2	157	/* Load/Store Support	    (37-41) */
+#define ICTRL	158
+
+/* Registers in the processor's internal memory map that we use.
+*/
+#define IMMR	0xff000000
+
+#define SYPCR	0x00000004
+#define BR0	0x00000100
+#define OR0	0x00000104
+#define BR1	0x00000108
+#define OR1	0x0000010c
+#define BR2	0x00000110
+#define OR2	0x00000114
+#define BR3	0x00000118
+#define OR3	0x0000011c
+#define BR4	0x00000120
+#define OR4	0x00000124
+
+#define MAR	0x00000164
+#define MCR	0x00000168
+#define MAMR	0x00000170
+#define MBMR	0x00000174
+#define MSTAT	0x00000178
+#define MPTPR	0x0000017a
+#define MDR	0x0000017c
+
+#define TBSCR	0x00000200
+#define TBREFF0	0x00000204
+
+#define PLPRCR	0x00000284
+
+#define curptr r2
+
+#define SYNC \
+	sync; \
+	isync
+
+/*
+ * Macros for storing registers into and loading registers from
+ * exception frames.
+ */
+#define SAVE_GPR(n, base)	stw	n,GPR0+4*(n)(base)
+#define SAVE_2GPRS(n, base)	SAVE_GPR(n, base); SAVE_GPR(n+1, base)
+#define SAVE_4GPRS(n, base)	SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
+#define SAVE_8GPRS(n, base)	SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
+#define SAVE_10GPRS(n, base)	SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
+#define REST_GPR(n, base)	lwz	n,GPR0+4*(n)(base)
+#define REST_2GPRS(n, base)	REST_GPR(n, base); REST_GPR(n+1, base)
+#define REST_4GPRS(n, base)	REST_2GPRS(n, base); REST_2GPRS(n+2, base)
+#define REST_8GPRS(n, base)	REST_4GPRS(n, base); REST_4GPRS(n+4, base)
+#define REST_10GPRS(n, base)	REST_8GPRS(n, base); REST_2GPRS(n+8, base)
+
+/*
+ * GCC sometimes accesses words at negative offsets from the stack
+ * pointer, although the SysV ABI says it shouldn't.  To cope with
+ * this, we leave this much untouched space on the stack on exception
+ * entry.
+ */
+#define STACK_UNDERHEAD	64
+
+#if 0	/* we don't use virtual addresses in PPCBOOT */
+#define tophys(rd,rs,rt)	addis	rd,rs,-KERNELBASE@h
+#define tovirt(rd,rs,rt)	addis	rd,rs,KERNELBASE@h
+#else
+#define tophys(rd,rs,rt)	mr	rd,rs
+#define tovirt(rd,rs,rt)	mr	rd,rs
+#endif
+
+/*
+ * Exception entry code.  This code runs with address translation
+ * turned off, i.e. using physical addresses.
+ * We assume sprg3 has the physical address of the current
+ * task's thread_struct.
+ */
+#define EXCEPTION_PROLOG	\
+	mtspr	SPRG0,r20;	\
+	mtspr	SPRG1,r21;	\
+	mfcr	r20;		\
+	tophys(r21,r1,r21);		/* use tophys(kernel sp) otherwise */ \
+	subi	r21,r21,INT_FRAME_SIZE+STACK_UNDERHEAD;	/* alloc exc. frame */\
+1:	stw	r20,_CCR(r21);		/* save registers */ \
+	stw	r22,GPR22(r21);	\
+	stw	r23,GPR23(r21);	\
+	mfspr	r20,SPRG0;	\
+	stw	r20,GPR20(r21);	\
+	mfspr	r22,SPRG1;	\
+	stw	r22,GPR21(r21);	\
+	mflr	r20;		\
+	stw	r20,_LINK(r21);	\
+	mfctr	r22;		\
+	stw	r22,_CTR(r21);	\
+	mfspr	r20,XER;	\
+	stw	r20,_XER(r21);	\
+	mfspr	r22,SRR0;	\
+	mfspr	r23,SRR1;	\
+	stw	r0,GPR0(r21);	\
+	stw	r1,GPR1(r21);	\
+	stw	r2,GPR2(r21);	\
+	stw	r1,0(r21);	\
+	tovirt(r1,r21,r1);		/* set new kernel sp */	\
+	SAVE_4GPRS(3, r21);
+/*
+ * Note: code which follows this uses cr0.eq (set if from kernel),
+ * r21, r22 (SRR0), and r23 (SRR1).
+ */
+
+/*
+ * Exception vectors.
+ *
+ * The data words for `hdlr' and `int_return' are initialized with
+ * OFFSET values only; they must be relocated first before they can
+ * be used!
+ */
+#define STD_EXCEPTION(n, label, hdlr)			\
+	. = n;						\
+label:							\
+	EXCEPTION_PROLOG;				\
+	lwz	r3,GOT(transfer_to_handler);		\
+	mtlr	r3;					\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;		\
+	li	r20,MSR_KERNEL;				\
+	blrl	; 					\
+.L_ ## label :						\
+	.long	hdlr - _start + EXC_OFF_SYS_RESET;	\
+	.long	int_return - _start + EXC_OFF_SYS_RESET
+
+
+#endif	/* __PPC_ASM_TMPL__ */
diff --git a/src/arch/ppc/include/ppcreg.h b/src/arch/ppc/include/ppcreg.h
new file mode 100644
index 0000000000..5ec0dd9417
--- /dev/null
+++ b/src/arch/ppc/include/ppcreg.h
@@ -0,0 +1,128 @@
+/* $Id$ */
+/* Copyright 2000  AG Electronics Ltd. */
+/* This code is distributed without warranty under the GPL v2 (see COPYING) */
+
+/* In the MSR, not all bits are interesting to us
+   13 - POW - Power management
+   14 - TGPR - temporary registers for page table routines
+   15 - ILE - Exception little endian
+   16 - EE  - External interrupts
+   17 - PR  - Privilege level
+   18 - FP  - Floating Point available
+   19 - ME  - Machine check exception enable
+   20 - FE0 - Floating exception mode 0
+   21 - SE  - Single step trace mode
+   22 - BE  - Branch trace enable
+   23 - FE1 - Floating exception mode 1
+   25 - IP  - Exception prefix
+   26 - IR  - Instruction address translation
+   27 - DR  - Data address translation
+   30 - RI  - Recoverable exception
+   31 - LE  - Little endian mode
+   MSR_MASK is the bits we do not change.
+   */
+
+#define MSR_MASK 0xfff8008c
+#define MSR_POW  0x00040000
+#define MSR_TGPR 0x00020000
+#define MSR_ILE  0x00010000
+#define MSR_EE   0x00008000
+#define MSR_PR   0x00004000
+#define MSR_FP   0x00002000
+#define MSR_ME   0x00001000
+#define MSR_FE0  0x00000800
+#define MSR_SE   0x00000400
+#define MSR_BE   0x00000200
+#define MSR_FE1  0x00000100
+#define MSR_IP   0x00000040
+#define MSR_IR   0x00000020
+#define MSR_DR   0x00000010
+#define MSR_RI   0x00000002
+#define MSR_LE   0x00000001
+
+#define MSR_DEFAULT (MSR_FP | MSR_IR | MSR_DR)
+
+/* We are interested in the following hid0 bits:
+   6  - ECLK  - Enable external test clock (603 only)
+   11 - DPM   - Turn on dynamic power management (603 only)
+   15 - NHR   - Not hard reset
+   16 - ICE   - Instruction cache enable
+   17 - DCE   - Data cache enable
+   18 - ILOCK - Instruction cache lock
+   19 - DLOCK - Data cache lock
+   20 - ICFI  - Instruction cache invalidate
+   21 - DCFI  - Data cache invalidate
+   24 - NOSER - Serial execution disable (604 only - turbo mode)
+   24 - SGE   - Store gathering enable (7410 only)
+   29 - BHT   - Branch history table (604 only)
+   
+   I made up the tags for the 604 specific bits, as they aren't
+   named in the 604 book.  The 603 book calls the invalidate bits
+   ICFI and DCI, and I have no idea why it isn't DCFI. Maybe IBM named
+   one, and Motorola named the other. */
+
+#define HID0_ECLK   0x02000000
+#define HID0_DPM    0x00100000
+#define HID0_NHR    0x00010000
+#define HID0_ICE    0x00008000
+#define HID0_DCE    0x00004000
+#define HID0_ILOCK  0x00002000
+#define HID0_DLOCK  0x00001000
+#define HID0_ICFI   0x00000800
+#define HID0_DCFI   0x00000400
+#define HID0_NOSER  0x00000080
+#define HID0_SGE    0x00000080
+#define HID0_BTIC   0x00000020
+#define HID0_BHT    0x00000004
+
+/*
+ * BAT defines
+ */
+
+/*
+ * BL field in upper BAT register
+ */
+#define BAT_BL_128K	0x00000000
+#define BAT_BL_256K	0x00000004
+#define BAT_BL_512K	0x0000000C
+#define BAT_BL_1M	0x0000001C
+#define BAT_BL_2M	0x0000003C
+#define BAT_BL_4M	0x0000007C
+#define BAT_BL_8M	0x000000FC
+#define BAT_BL_16M	0x000001FC
+#define BAT_BL_32M	0x000003FC
+#define BAT_BL_64M	0x000007FC
+#define BAT_BL_128M	0x00000FFC
+#define BAT_BL_256M	0x00001FFC
+
+/*
+ * Supervisor/user valid mode in upper BAT register
+ */
+#define BAT_VALID_SUPERVISOR	0x00000002
+#define BAT_VALID_USER		0x00000001
+#define BAT_INVALID		0x00000000
+
+/*
+ * WIMG bit setting in lower BAT register
+ */
+#define BAT_WRITE_THROUGH	0x00000040
+#define BAT_CACHE_INHIBITED	0x00000020
+#define BAT_COHERENT		0x00000010
+#define BAT_GUARDED		0x00000008
+
+/*
+ * Protection bits in lower BAT register
+ */
+#define BAT_NO_ACCESS	0x00000000
+#define BAT_READ_ONLY	0x00000001
+#define BAT_READ_WRITE	0x00000002
+
+#ifndef ASM
+unsigned __getmsr(void);
+void __setmsr(unsigned value);
+unsigned __gethid0(void);
+unsigned __gethid1(void);
+void __sethid0(unsigned value);
+unsigned __getpvr(void);
+#endif
+
diff --git a/src/arch/ppc/include/stddef.h b/src/arch/ppc/include/stddef.h
new file mode 100644
index 0000000000..2ea8ebb13c
--- /dev/null
+++ b/src/arch/ppc/include/stddef.h
@@ -0,0 +1,15 @@
+#ifndef PPC_STDDEF_H
+#define PPC_STDDEF_H
+
+typedef long ptrdiff_t;
+typedef unsigned long size_t;
+typedef long ssize_t;
+
+typedef int wchar_t;
+typedef unsigned int wint_t;
+
+#define NULL 0
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#endif /* PPC_STDDEF_H */
diff --git a/src/arch/ppc/include/stdint.h b/src/arch/ppc/include/stdint.h
new file mode 100644
index 0000000000..73da924b1e
--- /dev/null
+++ b/src/arch/ppc/include/stdint.h
@@ -0,0 +1,52 @@
+#ifndef PPC_STDINT_H
+#define PPC_STDINT_H
+
+/* Exact integral types */
+typedef unsigned char      uint8_t;
+typedef signed char        int8_t; 
+
+typedef unsigned short     uint16_t;
+typedef signed short       int16_t;
+
+typedef unsigned int       uint32_t;
+typedef signed int         int32_t;
+
+typedef unsigned long long uint64_t;
+typedef signed long long   int64_t;
+
+/* Small types */
+typedef unsigned char      uint_least8_t;
+typedef signed char        int_least8_t; 
+
+typedef unsigned short     uint_least16_t;
+typedef signed short       int_least16_t;
+
+typedef unsigned int       uint_least32_t;
+typedef signed int         int_least32_t;
+
+typedef unsigned long long uint_least64_t;
+typedef signed long long   int_least64_t;
+
+/* Fast Types */
+typedef unsigned char      uint_fast8_t;
+typedef signed char        int_fast8_t; 
+
+typedef unsigned int       uint_fast16_t;
+typedef signed int         int_fast16_t;
+
+typedef unsigned int       uint_fast32_t;
+typedef signed int         int_fast32_t;
+
+typedef unsigned long long uint_fast64_t;
+typedef signed long long   int_fast64_t;
+
+/* Types for `void *' pointers.  */
+typedef int                intptr_t;
+typedef unsigned int       uintptr_t;
+
+/* Largest integral types */
+typedef long long int      intmax_t;
+typedef unsigned long long uintmax_t;
+
+
+#endif /* PPC_STDINT_H */
diff --git a/src/arch/ppc/include/timer.h b/src/arch/ppc/include/timer.h
new file mode 100644
index 0000000000..9a2328f7cd
--- /dev/null
+++ b/src/arch/ppc/include/timer.h
@@ -0,0 +1,13 @@
+/* $Id$ */
+/* Copyright 2000  AG Electronics Ltd. */
+/* This code is distributed without warranty under the GPL v2 (see COPYING) */
+
+#ifndef _TIMER_H
+#define __TIMER_H
+
+unsigned get_hz(void);
+unsigned ticks_since_boot(void);
+void sleep_ticks(unsigned);
+void udelay(int);
+
+#endif