diff options
| author | Greg Watson <gwatson@lanl.gov> | 2005-10-19 21:55:47 +0000 |
|---|---|---|
| committer | Greg Watson <gwatson@lanl.gov> | 2005-10-19 21:55:47 +0000 |
| commit | aa9ef4195a12feb7b9ccc9bc9dc24806df13c022 (patch) | |
| tree | b4eadf19b28cc70e459de1aac9a5d99d46735d68 /src/arch/ppc/include/ppc970.h | |
| parent | 5fc3aa73eb5e978bcd37061c49932b10e80c45c2 (diff) | |
trying to compile...
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/arch/ppc/include/ppc970.h')
| -rw-r--r-- | src/arch/ppc/include/ppc970.h | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/src/arch/ppc/include/ppc970.h b/src/arch/ppc/include/ppc970.h index 7358d52e44..5c0f884972 100644 --- a/src/arch/ppc/include/ppc970.h +++ b/src/arch/ppc/include/ppc970.h @@ -18,16 +18,30 @@ | 13-Oct-03 Created MPT +----------------------------------------------------------------------------*/ -#ifndef _sys_as_archppc970_h_ -#define _sys_as_archppc970_h_ +#ifndef _PPC970_H_ +#define _PPC970_H_ /*----------------------------------------------------------------------------+ -| PVR value. +| When timers are running based on CPU speed this is the timer to CPU frequency +| ratio. +----------------------------------------------------------------------------*/ -#define PVR_970_DD1 0x00391100 -#define PVR_970FX_DD2 0x003C0200 -#define PVR_970FX_DD2_1 0x003C0201 -#define PVR_970FX_DD3 0x003C0300 +#define PPC970_TB_RATIO 8 + +/*----------------------------------------------------------------------------+ +| Cache line size. ++----------------------------------------------------------------------------*/ +#define CACHE_LINE_SIZE_L1 128 +#define CACHE_LINE_SIZE_L2 128 + +/*----------------------------------------------------------------------------+ +| SLB size. ++----------------------------------------------------------------------------*/ +#define SLB_SIZE 64 + +/*----------------------------------------------------------------------------+ +| TLB size. ++----------------------------------------------------------------------------*/ +#define TLB_SIZE 1024 /*----------------------------------------------------------------------------+ | Special Purpose Registers. Xer (64), lr (64), ctr (64), srr0 (64), srr1 (64) @@ -225,4 +239,4 @@ #define SRR1_ITLB_RELOA 0x00000000000C0000 #define SRR1_RI 0x0000000000000002 -#endif /* _sys_as_archppc970_h_ */ +#endif /* _PPC970_H_ */ |