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| author | Furquan Shaikh <furquan@google.com> | 2016-08-11 12:39:54 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-08-15 23:54:02 +0200 |
| commit | e4cc4733ebd4c6fc77de5f0a9963e9a938e57e5d (patch) | |
| tree | 4d41895374ae66c2eac19015c3357b30cff5e4ab /src/arch/mips/cache.c | |
| parent | c3b024e99baf8d27ae1554b0dd0ef061f82b64ee (diff) | |
reef: Increase TSR2 threshold to 100
This is a temporary work-around since the current threshold of 70 on
TSR2 results in thermal trip and shutdown while the kernel is
booting. Changing this threshold to 100 allows kernel to boot up to
userspace. Following values were read:
$ cat /sys/class/thermal/thermal_zone4/temp
81800
$ cat /sys/class/thermal/thermal_zone4/type
TSR2
BUG=chrome-os-partner:56155
BRANCH=None
TEST=Boots to OS.
Change-Id: I951553ed4c93b02239a51a0d3036e4a750eea04b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16156
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch/mips/cache.c')
0 files changed, 0 insertions, 0 deletions