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| author | Werner Zeh <werner.zeh@siemens.com> | 2019-03-12 07:07:50 +0100 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2019-03-14 07:47:54 +0000 |
| commit | fedb36e3c849685e2dbf1b6feb2e936a559f9bfb (patch) | |
| tree | b2a36f4626b1ea49762dd6e664995acafe8a2c41 /src/arch/mips/bootblock_simple.c | |
| parent | 423adfb0d3d84bea9e862cd068a530146aacac60 (diff) | |
x86/acpi: Only sort CPU IDs if more than one available
Sorting makes only sense if there are at least two entries available.
Change-Id: If40638bf1fe24dcff4b7839967445fb4218184f8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/arch/mips/bootblock_simple.c')
0 files changed, 0 insertions, 0 deletions