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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-03-06 01:49:27 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-09 17:04:21 +0100 |
| commit | 0819a47d14e8c933dab7089a41625f043778a4c7 (patch) | |
| tree | 4b65ca9caa0435c700d5808bba79ab9e535636f8 /src/arch/mips/Makefile.inc | |
| parent | 5ad9acaba667cd7e53bb654996967427f0afb4ba (diff) | |
northbridge/intel/gm45: Use TSC for ramstage timer per default
This is a step towards isolating the timer drivers.
Change-Id: I4c9349054be0cf520cd4407be9fb393b664223a4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13922
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/arch/mips/Makefile.inc')
0 files changed, 0 insertions, 0 deletions