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authorEric Biederman <ebiederm@xmission.com>2003-07-19 04:28:22 +0000
committerEric Biederman <ebiederm@xmission.com>2003-07-19 04:28:22 +0000
commit9b4336cf418d22551bea09d93e1cee79281b110e (patch)
tree3f1e24216c11918644a98fd1e46e2fdb40fd12fe /src/arch/i386/smp
parentfe4414587a4466b848184b8837d4c5a280949824 (diff)
- Major cleanup of the bootpath
- Changes to allow more code to be compiled both ways - Working SMP support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/arch/i386/smp')
-rw-r--r--src/arch/i386/smp/secondary.S76
-rw-r--r--src/arch/i386/smp/start_stop.c1
2 files changed, 77 insertions, 0 deletions
diff --git a/src/arch/i386/smp/secondary.S b/src/arch/i386/smp/secondary.S
new file mode 100644
index 0000000000..78c55764b0
--- /dev/null
+++ b/src/arch/i386/smp/secondary.S
@@ -0,0 +1,76 @@
+#include <arch/asm.h>
+#include <arch/intel.h>
+#include <cpu/p6/mtrr.h>
+#include <cpu/p6/apic.h>
+ .text
+ .globl _secondary_start
+ .balign 4096
+_secondary_start:
+ .code16
+ cli
+ xorl %eax, %eax
+ movl %eax, %cr3 /* Invalidate TLB*/
+
+ /* On hyper threaded cpus invalidating the cache here is
+ * very very bad. Don't.
+ */
+
+ /* setup the data segment */
+ movw %cs, %ax
+ movw %ax, %ds
+
+ data32 lgdt gdtaddr - _secondary_start
+
+ movl %cr0, %eax
+ andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
+ orl $0x60000001, %eax /* CD, NW, PE = 1 */
+ movl %eax, %cr0
+
+ ljmpl $0x10, $1f
+1:
+ .code32
+ movw $0x18, %ax
+ movw %ax, %ds
+ movw %ax, %es
+ movw %ax, %ss
+ movw %ax, %fs
+ movw %ax, %gs
+
+ /* Enable the local apic, and map it where we expext it */
+ movl $APIC_BASE_MSR, %ecx
+ rdmsr
+ orl $APIC_BASE_MSR_ENABLE, %eax
+ andl $(~APIC_BASE_MSR_ADDR_MASK), %eax
+ orl $APIC_DEFAULT_BASE, %eax
+ wrmsr
+
+ /* Get the apic_id */
+ movl (APIC_ID + APIC_DEFAULT_BASE), %edi
+ shrl $24, %edi
+
+ /* Get the cpu index (MAX_CPUS on error) */
+ movl $-4, %ebx
+1: addl $4, %ebx
+ cmpl $(MAX_CPUS << 2), %ebx
+ je 2
+ cmpl %edi, initial_apicid(%ebx)
+ jne 1b
+2: shrl $2, %ebx
+
+ /* set the stack pointer */
+ movl $_estack, %esp
+ movl %ebx, %eax
+ movl $STACK_SIZE, %ebx
+ mull %ebx
+ subl %eax, %esp
+
+ call secondary_cpu_init
+1: hlt
+ jmp 1b
+
+gdtaddr:
+ .word gdt_limit /* the table limit */
+ .long gdt /* we know the offset */
+
+
+.code32
diff --git a/src/arch/i386/smp/start_stop.c b/src/arch/i386/smp/start_stop.c
index 018ec30705..bb8868a8d9 100644
--- a/src/arch/i386/smp/start_stop.c
+++ b/src/arch/i386/smp/start_stop.c
@@ -3,6 +3,7 @@
#include <cpu/p6/apic.h>
#include <delay.h>
#include <string.h>
+#include <console/console.h>
#ifndef START_CPU_SEG
#define START_CPU_SEG 0x90000