- To reduce confuse rename the parts of linuxbios bios that run from

  ram linuxbios_ram instead of linuxbios_c and linuxbios_payload...
- Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86
- ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB.
- Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work.
- Start using romcc's built in preprocessor (This will simplify header compiler checks)
- Add helper functions for examining all of the resources
- Remove debug strings from chip.h
- Add llshell to src/arch/i386/llshell (Sometime later I can try it...)
- Add the ability to catch exceptions on x86
- Add gdb_stub support to x86
- Removed old cpu options
- Added an option so we can detect movnti support
- Remove some duplicate definitions from pci_ids.h
- Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic
- Minor romcc bug fixes


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 25 insertions, 0 deletions

diff --git a/src/arch/i386/llshell/readme.linuxbios b/src/arch/i386/llshell/readme.linuxbios
new file mode 100644
index 0000000000..fb23d1a9d4
--- /dev/null
+++ b/src/arch/i386/llshell/readme.linuxbios
@@ -0,0 +1,25 @@
+
+1) Include llshell.inc in your northbridge Config file
+2) In raminit.inc (or whatever), make a jmp out to low_level_shell, setting
+   a return label in %esp.
+For example:
+ram_set_registers:
+
+	mov $llshell_ret1,%esp
+	jmp low_level_shell
+llshell_ret1:
+
+        /* Disable and invalidate the cache */
+        invd
+        mov %cr0, %eax
+        ....
+3) Optionally, comment out two lines in ramtest.inc:
+5:
+        CONSOLE_INFO_TX_STRING($rt_toomany)
+        // intel_chip_post_macro(0xf1)
+        // jmp  .Lhlt
+otherwise, a ramtest failure will hang
+
+4) build and flash as normal
+If it worked, the speaker will beep, and you'll get a shell.
+Type help or ? at the prompt for a list of commands.