- Modify the freebios tree so the pci config space api is mostly in sync between

  code that runs without ram and code that runs with ram.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 0 insertions, 51 deletions

diff --git a/src/arch/i386/include/arch/romcc_io.h b/src/arch/i386/include/arch/romcc_io.h
index 677133f2a9..7d3d50e39c 100644
--- a/src/arch/i386/include/arch/romcc_io.h
+++ b/src/arch/i386/include/arch/romcc_io.h
@@ -61,56 +61,6 @@ static void wrmsr(unsigned long index, msr_t msr)
 #define PCI_ID(VENDOR_ID, DEVICE_ID) \
 	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
 
-#if 0
-static unsigned char pci_read_config8(unsigned addr)
-{
-	outl(0x80000000 | (addr & ~3), 0xCF8);
-	return inb(0xCFC + (addr & 3));
-}
-
-static unsigned short pci_read_config16(unsigned addr)
-{
-	outl(0x80000000 | (addr & ~3), 0xCF8);
-	return inw(0xCFC + (addr & 2));
-}
-
-static unsigned int pci_read_config32(unsigned addr)
-{
-	outl(0x80000000 | (addr & ~3), 0xCF8);
-	return inl(0xCFC);
-}
-
-static void pci_write_config8(unsigned addr, unsigned char value)
-{
-	outl(0x80000000 | (addr & ~3), 0xCF8);
-	outb(value, 0xCFC + (addr & 3));
-}
-
-static void pci_write_config16(unsigned addr, unsigned short value)
-{
-	outl(0x80000000 | (addr & ~3), 0xCF8);
-	outw(value, 0xCFC + (addr & 2));
-}
-
-static void pci_write_config32(unsigned addr, unsigned int value)
-{
-	outl(0x80000000 | (addr & ~3), 0xCF8);
-	outl(value, 0xCFC);
-}
-
-static unsigned pci_locate_device(unsigned pci_id, unsigned addr)
-{
-	addr &= ~0xff;
-	for(; addr <= PCI_ADDR(255, 31, 7, 0); addr += PCI_ADDR(0,0,1,0)) {
-		unsigned int id;
-		id = pci_read_config32(addr);
-		if (id == pci_id) {
-			return addr;
-		}
-	}
-	return ~0U;
-}
-#else
 typedef unsigned device_t;
 
 static unsigned char pci_read_config8(device_t dev, unsigned where)
@@ -174,4 +124,3 @@ static device_t pci_locate_device(unsigned pci_id, device_t dev)
 	return PCI_DEV_INVALID;
 }
 
-#endif