Snow bootblock (bloated/debug version)

This is the bloated Snow bootblock which includes:
- SPI driver
- UART, including requisite I2C, Maxim PMIC, and clock config code.
- Adjustments for magic offsets (id section, stack pointer address)

This is just a temporary solution until we have romstage loading.
Once that happens, we'll rip out all but the code necessary for
copying SPI ROM content into SRAM.

Change-Id: I2a11e272eb9b6f626b5d9783eabb4a720a1d06be
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2170
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/src/arch/armv7/lib/id.lds b/src/arch/armv7/lib/id.lds
index f2b794a194..b521f3956b 100644
--- a/src/arch/armv7/lib/id.lds
+++ b/src/arch/armv7/lib/id.lds
@@ -1,6 +1,6 @@
 SECTIONS {
 	/* FIXME: determine a sensible location... */
-	. = (0x2024000) - (__id_end - __id_start);
+	. = (0x2026400);
 	.id (.): {
 		*(.id)
 	}