WIP: Initial ARMv7 architecture implementation in coreboot

The first ARMv7 CPU we're going to support is the Exynos 5250
used in the Google Snow ChromeBook.

Change-Id: I4de8433bbc6202eb8fef2556a11186a3376d411b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2004
Tested-by: build bot (Jenkins)

1 files changed, 26 insertions, 0 deletions

diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc
new file mode 100644
index 0000000000..bdf6a64ffb
--- /dev/null
+++ b/src/arch/armv7/lib/Makefile.inc
@@ -0,0 +1,26 @@
+romstage-y += cache_v7.c
+romstage-y += cache-cp15.c
+romstage-y += div0.c
+romstage-y += div64.S
+romstage-y += hang_spl.c
+romstage-y += romstage_console.c
+romstage-y += syslib.c
+
+#ramstage-y += printk_init.c
+#romstage-y += walkcbfs.S
+
+ramstage-y += c_start.S
+
+#ramstage-y += div.c
+ramstage-y += div0.c
+ramstage-y += div64.S
+ramstage-y += hang_spl.c
+#ramstage-y += interrupts.c
+#ramstage-y += memcpy.S
+#ramstage-y += memset.S
+#ramstage-y += reset.c
+ramstage-y += syslib.c
+
+#FIXME(dhendrix): should this be a config option?
+romstage-y += eabi_compat.c
+ramstage-y += eabi_compat.c