diff options
author | David Hendricks <dhendrix@chromium.org> | 2013-03-19 17:32:54 -0700 |
---|---|---|
committer | David Hendricks <dhendrix@chromium.org> | 2013-03-21 05:13:49 +0100 |
commit | a54efdcf8cd8cc0f5f879fdf229b2e479bf0bcd1 (patch) | |
tree | beb1520be8f38786b228c119e2dbf243869f7355 /src/arch/armv7/include | |
parent | 2138afe943edec9237790583bc1b699436fd4da4 (diff) |
armv7: cosmetic changes to new cache code
This clarifies and/or fixes formatting of some comments and
alphabetizes some function prototypes and inlines. It also
corrects references to "modified virtual address" (MVA).
Change-Id: Ibcdda4febf915cc4a1996a5bbb4ffecbcb50a324
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2869
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch/armv7/include')
-rw-r--r-- | src/arch/armv7/include/arch/cache.h | 38 |
1 files changed, 22 insertions, 16 deletions
diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 643da7c69e..31ed34579a 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -25,6 +25,8 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. + * + * cache.h: Cache maintenance API for ARMv7 */ #ifndef ARMV7_CACHE_H @@ -128,12 +130,6 @@ static inline void dccisw(uint32_t val) asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val)); } -/* data cache invalidate by set/way */ -static inline void dcisw(uint32_t val) -{ - asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val)); -} - /* data cache clean by MVA to PoC */ static inline void dccmvac(unsigned long mva) { @@ -146,6 +142,12 @@ static inline void dcimvac(unsigned long mva) asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva)); } +/* data cache invalidate by set/way */ +static inline void dcisw(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val)); +} + /* instruction cache invalidate all by PoU */ static inline void iciallu(void) { @@ -210,25 +212,29 @@ static inline void write_sctlr(unsigned int val) * Cache maintenance API */ -/* invalidate all TLBs */ -void tlb_invalidate_all(void); - -/* clean and invalidate entire dcache on current level (given by CCSELR) */ +/* dcache clean and invalidate all (on current level given by CCSELR) */ void dcache_clean_invalidate_all(void); -/* invalidate entire dcache on current level (given by CCSELR) */ -void dcache_invalidate_all(void); - -/* invalidate and clean dcache by machine virtual address to PoC */ +/* dcache clean and invalidate by modified virtual address to PoC */ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); -/* invalidate entire icache on current level (given by CSSELR) */ +/* dcache invalidate all (on current level given by CCSELR) */ +void dcache_invalidate_all(void); + +/* icache invalidate all (on current level given by CSSELR) */ void icache_invalidate_all(void); +/* tlb invalidate all */ +void tlb_invalidate_all(void); + +/* + * Generalized setup/init functions + */ + /* invalidate all caches on ARMv7 */ void armv7_invalidate_caches(void); -/* MMU setup by machine virtual address */ +/* MMU setup by modified virtual address */ void mmu_setup_by_mva(unsigned long start, unsigned long size); #endif /* ARMV7_CACHE_H */ |