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authorDavid Hendricks <dhendrix@chromium.org>2013-03-21 21:58:50 -0700
committerRonald G. Minnich <rminnich@gmail.com>2013-03-26 00:10:31 +0100
commitf9be756b559ccc567e5412c85b5ded98f19617e7 (patch)
tree753c8f5d36b7023766ae9f11561ce86183a13e13 /src/arch/armv7/bootblock_simple.c
parent04d352db41522b3c7aec2ce574ff90484bc0ad8a (diff)
armv7: add new dcache and MMU setup functions
This adds new MMU setup code. Most notably, this version uses cbmem_add() to determine the translation table base address, which in turn is necessary to ensure payloads which wipe memory can tell which regions to wipe out. TODOs: - Finish cleaning up references to old cache/MMU stuff - Add L2 setup (from exynos_cache.c) - Set up ranges dynamically rather than in ramstage's main(). Change-Id: Iba5295a801e8058a3694e4ec5b94bbe9a69d3ee6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2877 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/armv7/bootblock_simple.c')
-rw-r--r--src/arch/armv7/bootblock_simple.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c
index ad25b41316..f6134f75fb 100644
--- a/src/arch/armv7/bootblock_simple.c
+++ b/src/arch/armv7/bootblock_simple.c
@@ -53,12 +53,14 @@ void main(void)
armv7_invalidate_caches();
/*
- * Re-enable caches and branch prediction. MMU will be set up later.
+ * Re-enable icache and branch prediction. MMU and dcache will be
+ * set up later.
+ *
* Note: If booting from USB, we need to disable branch prediction
* before copying from USB into RAM (FIXME: why?)
*/
sctlr = read_sctlr();
- sctlr |= SCTLR_C | SCTLR_Z | SCTLR_I;
+ sctlr |= SCTLR_Z | SCTLR_I;
write_sctlr(sctlr);
if (boot_cpu()) {