armv7: update coreboot tables for armv7

This is a first-pass attempt at cleaning up the coreboot tables
for ARM. The most noticable difference is that there is no longer
both a high and a low table.

Change-Id: I5ba87ad57bf9a697b733511182c0326825071617
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2329
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 18 insertions, 42 deletions

diff --git a/src/arch/armv7/boot/tables.c b/src/arch/armv7/boot/tables.c
index 07c56354c8..813eaeab5d 100644
--- a/src/arch/armv7/boot/tables.c
+++ b/src/arch/armv7/boot/tables.c
@@ -28,6 +28,10 @@
 #include <cbmem.h>
 #include <lib.h>
 
+/*
+ * TODO: "High" tables are a convention used on x86. Maybe we can
+ * clean up that naming at some point.
+ */
 uint64_t high_tables_base = 0;
 uint64_t high_tables_size;
 
@@ -37,58 +41,30 @@ void cbmem_arch_init(void)
 
 struct lb_memory *write_tables(void)
 {
-	unsigned long low_table_start, low_table_end;
-	unsigned long rom_table_start, rom_table_end;
-
-	/* Even if high tables are configured, some tables are copied both to
-	 * the low and the high area, so payloads and OSes don't need to know
-	 * about the high tables.
-	 */
-	unsigned long high_table_pointer;
+	unsigned long table_pointer;
 
 	if (!high_tables_base) {
-		printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n");
+		printk(BIOS_ERR, "ERROR: coreboot_tables_base is not set.\n");
 		// Are there any boards without?
 		// Stepan thinks we should die() here!
 	}
 
-	printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base);
-
-	rom_table_start = 0xf0000;
-	rom_table_end =   0xf0000;
-
-	/* Start low addr at 0x500, so we don't run into conflicts with the BDA
-	 * in case our data structures grow beyound 0x400. Only multiboot, GDT
-	 * and the coreboot table use low_tables.
-	 */
-	low_table_start = 0;
-	low_table_end = 0x500;
+	printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base);
 
-#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
 	post_code(0x9d);
 
-	high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE);
-
-	if (high_table_pointer) {
-		unsigned long new_high_table_pointer;
-
-		/* Also put a forwarder entry into 0-4K */
-		new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end,
-				high_tables_base, high_table_pointer);
-
-		if (new_high_table_pointer > (high_table_pointer +
-					MAX_COREBOOT_TABLE_SIZE))
+	table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE,
+						MAX_COREBOOT_TABLE_SIZE);
+	if (table_pointer) {
+		unsigned long new_table_pointer;
+		new_table_pointer = write_coreboot_table(table_pointer,
+							high_tables_size);
+		if (table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) {
 			printk(BIOS_ERR, "%s: coreboot table didn't fit (%lx)\n",
-				   __func__, new_high_table_pointer -
-				   high_table_pointer);
-
-                printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
-				new_high_table_pointer - high_table_pointer);
-	} else {
-		/* The coreboot table must be in 0-4K or 960K-1M */
-		rom_table_end = write_coreboot_table(
-				     low_table_start, low_table_end,
-				     rom_table_start, rom_table_end);
+				   __func__, new_table_pointer - table_pointer);
+		}
+		printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
+			new_table_pointer - table_pointer);
 	}
 
 	post_code(0x9e);