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authorMaxim Polyakov <max.senia.poliak@gmail.com>2020-09-08 09:56:21 +0300
committerPatrick Georgi <pgeorgi@google.com>2020-09-21 08:08:51 +0000
commitf8c147431e6207b9f3508a7da202fe6dfb04e5a4 (patch)
tree431aee7bba0f844fb0d85d3c172e954f6a9f8437 /src/arch/arm
parent22bf6fbcba54eedf8623a3141aad49bb82ba4add (diff)
mb/razer/blade_stealth_kbl: 1/3 Decode raw register values
Use the intelp2m utility [1,2] with -adv options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... ./intelp2m -fld cb -t 1 -file ../../src/mainboard/razer/ blade_stealth_kbl/gpio.h This is part of the patch set "mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m": CB:43857 - 1/3 Decode raw register values CB:43858 - 2/3 Exclude fields for PAD_CFG CB:43411 - 3/3 Convert field macros to PAD_CFG Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical. [1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643 Change-Id: I7c4a29f87b56c5ec7e4b74274ae677c4c08c2e8c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Mimoja <coreboot@mimoja.de>
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