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authorDuncan Laurie <dlaurie@chromium.org>2016-06-27 10:57:13 -0700
committerDuncan Laurie <dlaurie@chromium.org>2016-07-02 01:18:22 +0200
commitff8bce0a5f53652d4d26cb501159e8711f79eb9b (patch)
treea66528533f3f26c959f7a2eed1b7c1d707900af4 /src/arch/arm
parent02fcc887829bc0bf4e98f591de2a199d6a69f2ba (diff)
soc/intel/apollolake: Add support for LPSS I2C driver
Support the I2C interfaces on this SOC using the Intel common lpss_i2c driver. The controllers are supported in pre-ram environments by setting a temporary base address in bootblock and in ramstage using the naturally enumerated base address. The base speed of this controller is 133MHz and the SCL/SDA timing values that are reported to the OS are calculated using that clock. This was tested on a google/reef board doing I2C transactions to the trackpad both in verstage and in ramstage. Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15480 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/arm')
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