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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-18 00:19:06 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-19 19:30:40 +0000
commit6766f4fd046604e6376c9769cd5f8357dec6a80a (patch)
treed373064f4d454c9c8a4be15421df8504e55b0dbc /src/arch/arm64/ramdetect.c
parent23c1c4e153e8f1311b2e04a19a7e0c66d648e972 (diff)
arch/x86: Fix S3 resume without stage cache
It was possible to have NO_STAGE_CACHE=n and at the same time have TSEG_STAGE_CACHE=n and CBMEM_STAGE_CACHE=n. This resulted with a failing attempt to load STAGE_POSTCAR from the stage cache, but not loading it from CBFS either. Make it a three-way choice between different STAGE_CACHE options. For AGESA disable CBMEM_STAGE_CACHE by default, as it is no longer needed to have functional ACPI S3 resume and it is not allowed se use keyword select for symbols inside choice blocks. Change-Id: I0da3e1cf4c92817ffabbb02eda3476ecdfdfa278 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37683 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/arm64/ramdetect.c')
0 files changed, 0 insertions, 0 deletions