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authorJoseph Lo <josephl@nvidia.com>2015-04-15 10:09:50 +0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-27 07:44:59 +0200
commitc38d3e8131b0f6ed7e576d1a66ac9513b1810f27 (patch)
tree73c0532239b8202b74d24cb8efd6b0281b8bd807 /src/arch/arm64/include/armv8
parentc4301f79691995dfedb56cb3e20adea3ecd8f596 (diff)
arm64: implement CPU power down sequence as per A57/A53/A72 TRM
Implement the individual core powerdown sequence as per Cortex-A57/A53/A72 TRM. Based-on-the-work-by: Varun Wadekar <vwadekar@nvidia.com> BRANCH=none BUG=none TEST=boot on smaug/foster, verify the cpu_on/off is ok as well Change-Id: I4719fcbe86b35f9b448d274e1732da5fc75346b0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b6bdcc12150820dfad28cef3af3d8220847c5d74 Original-Change-Id: I65abab8cda55cfe7a0c424f3175677ed5e3c2a1c Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265827 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9980 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/arch/arm64/include/armv8')
-rw-r--r--src/arch/arm64/include/armv8/arch/cpu.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h
index 14635e39c0..4e15209be0 100644
--- a/src/arch/arm64/include/armv8/arch/cpu.h
+++ b/src/arch/arm64/include/armv8/arch/cpu.h
@@ -187,4 +187,18 @@ void arm64_cpu_startup_resume(void);
*/
void arm64_arch_timer_init(void);
+/*
+ * The cortex_a57_cpu_power_down sequence as per A57/A53/A72 TRM.
+ * L2 flush by HW(0) or SW(1), if system/HW driven L2 flush is supported.
+ */
+#define NO_L2_FLUSH 0
+#define L2_FLUSH_HW 0
+#define L2_FLUSH_SW 1
+
+#if IS_ENABLED(CONFIG_ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT)
+void cortex_a57_cpu_power_down(int l2_flush);
+#else
+static inline void cortex_a57_cpu_power_down(int l2_flush) {}
+#endif
+
#endif /* __ARCH_CPU_H__ */