diff options
| author | Joseph Lo <josephl@nvidia.com> | 2015-04-15 10:09:50 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-27 07:44:59 +0200 |
| commit | c38d3e8131b0f6ed7e576d1a66ac9513b1810f27 (patch) | |
| tree | 73c0532239b8202b74d24cb8efd6b0281b8bd807 /src/arch/arm64/cpu/cortex_a57.h | |
| parent | c4301f79691995dfedb56cb3e20adea3ecd8f596 (diff) | |
arm64: implement CPU power down sequence as per A57/A53/A72 TRM
Implement the individual core powerdown sequence as per
Cortex-A57/A53/A72 TRM.
Based-on-the-work-by:
Varun Wadekar <vwadekar@nvidia.com>
BRANCH=none
BUG=none
TEST=boot on smaug/foster, verify the cpu_on/off is ok as well
Change-Id: I4719fcbe86b35f9b448d274e1732da5fc75346b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b6bdcc12150820dfad28cef3af3d8220847c5d74
Original-Change-Id: I65abab8cda55cfe7a0c424f3175677ed5e3c2a1c
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/265827
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9980
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/arch/arm64/cpu/cortex_a57.h')
| -rw-r--r-- | src/arch/arm64/cpu/cortex_a57.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm64/cpu/cortex_a57.h b/src/arch/arm64/cpu/cortex_a57.h index 9e66f4d7ca..9e12e8b41f 100644 --- a/src/arch/arm64/cpu/cortex_a57.h +++ b/src/arch/arm64/cpu/cortex_a57.h @@ -23,4 +23,10 @@ #define CPUECTLR_EL1 S3_1_c15_c2_1 #define SMPEN_SHIFT 6 +/* Cortex MIDR[15:4] PN */ +#define CORTEX_A53_PN 0xd03 + +/* Double lock control bit */ +#define OSDLR_DBL_LOCK_BIT 1 + #endif /* __ARCH_ARM64_CORTEX_A57_H__ */ |