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authorRaul E Rangel <rrangel@chromium.org>2021-04-06 15:41:22 -0600
committerPatrick Georgi <pgeorgi@google.com>2021-04-08 06:48:22 +0000
commit2ff76be15cf21b8e9af298e797ee75732af31838 (patch)
treed68f00bee66eb88ecdbbdb1e1849608d1279d1a8 /src/arch/arm64/armv8
parent3db49929bd7d755aad920ae6b8757bba57864989 (diff)
soc/amd/common: Add PM_ESPI_INTR_CTRL
This register is used for masking/unmasking eSPI IRQs. BUG=none TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia209539b2e0ce390e227757b16c2969b9124a845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52142 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/arm64/armv8')
0 files changed, 0 insertions, 0 deletions