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authorFurquan Shaikh <furquan@google.com>2014-06-11 14:48:37 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-02-25 20:01:44 +0100
commit26a8747ccaa1bf799cfb03c8ccaaf4205196f108 (patch)
treeeaef5106fe8ffff05a54b81602e1fdcb65195770 /src/arch/arm64/armv8/lib/tlb.c
parent595a40cfc92baecca9c58a7a95ae38ce72582f39 (diff)
coreboot arm64: Add library for system access
Add support for library functions required to access different system registers: 1) PSTATE and special purpose registers 2) System control registers 3) Cache-related registers 4) TLB maintenance registers 5) Misc barrier related functions BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I8809ca2b67b8e560b34577cda1483ee009a1d71a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203490 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 5da840c5d1f3d8fdf8cc0d7c44772bf0cef03fbb) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Get the library and the GPL license in a single commit. Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4753a6b0d13a6f7515243bfa8e749e250fdd749d Reviewed-on: http://review.coreboot.org/8465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/arch/arm64/armv8/lib/tlb.c')
-rw-r--r--src/arch/arm64/armv8/lib/tlb.c75
1 files changed, 75 insertions, 0 deletions
diff --git a/src/arch/arm64/armv8/lib/tlb.c b/src/arch/arm64/armv8/lib/tlb.c
new file mode 100644
index 0000000000..36d1e70a4a
--- /dev/null
+++ b/src/arch/arm64/armv8/lib/tlb.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * tlb.c: System intructions for TLB maintenance.
+ * Reference: ARM Architecture Reference Manual, ARMv8-A edition
+ */
+
+#include <stdint.h>
+
+#include <arch/lib_helpers.h>
+
+/* TLBIALL */
+void tlbiall_el1(void)
+{
+ __asm__ __volatile__("tlbi alle1\n\t" : : : "memory");
+}
+
+void tlbiall_el2(void)
+{
+ __asm__ __volatile__("tlbi alle2\n\t" : : : "memory");
+}
+
+void tlbiall_el3(void)
+{
+ __asm__ __volatile__("tlbi alle3\n\t" : : : "memory");
+}
+
+void tlbiall_current(void)
+{
+ SWITCH_CASE_TLBI(tlbiall);
+}
+
+/* TLBIALLIS */
+void tlbiallis_el1(void)
+{
+ __asm__ __volatile__("tlbi alle1is\n\t" : : : "memory");
+}
+
+void tlbiallis_el2(void)
+{
+ __asm__ __volatile__("tlbi alle2is\n\t" : : : "memory");
+}
+
+void tlbiallis_el3(void)
+{
+ __asm__ __volatile__("tlbi alle3is\n\t" : : : "memory");
+}
+
+void tlbiallis_current(void)
+{
+ SWITCH_CASE_TLBI(tlbiallis);
+}
+
+/* TLBIVAA */
+void tlbivaa_el1(uint64_t va)
+{
+ __asm__ __volatile__("tlbi vaae1, %0\n\t" : : "r" (va) : "memory");
+}