diff options
author | Julius Werner <jwerner@chromium.org> | 2018-08-03 17:14:45 -0700 |
---|---|---|
committer | Julius Werner <jwerner@chromium.org> | 2018-08-10 04:16:25 +0000 |
commit | 0c5f61a01c3ebaa1c19f9a20d20d4b1353648d7c (patch) | |
tree | b200a6be0cbc43adfd25d6778afce750ae81739c /src/arch/arm64/armv8/lib/tlb.c | |
parent | 73be9dd82c033a9bce3fc7ff11dab453e9cfde82 (diff) |
arm64: Drop checks for current exception level, hardcode EL3 assumption
When we first created the arm64 port, we weren't quite sure whether
coreboot would always run in EL3 on all platforms. The AArch64 A.R.M.
technically considers this exception level optional, but in practice all
SoCs seem to support it. We have since accumulated a lot of code that
already hardcodes an implicit or explicit assumption of executing in EL3
somewhere, so coreboot wouldn't work on a system that tries to enter it
in EL1/2 right now anyway.
However, some of our low level support libraries (in particular those
for accessing architectural registers) still have provisions for
running at different exception levels built-in, and often use switch
statements over the current exception level to decide which register to
access. This includes an unnecessarily large amount of code for what
should be single-instruction operations and precludes further
optimization via inlining.
This patch removes any remaining code that dynamically depends on the
current exception level and makes the assumption that coreboot executes
at EL3 official. If this ever needs to change for a future platform, it
would probably be cleaner to set the expected exception level in a
Kconfig rather than always probing it at runtime.
Change-Id: I1a9fb9b4227bd15a013080d1c7eabd48515fdb67
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/arm64/armv8/lib/tlb.c')
-rw-r--r-- | src/arch/arm64/armv8/lib/tlb.c | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/src/arch/arm64/armv8/lib/tlb.c b/src/arch/arm64/armv8/lib/tlb.c index d04afcf4ad..b40fb8f135 100644 --- a/src/arch/arm64/armv8/lib/tlb.c +++ b/src/arch/arm64/armv8/lib/tlb.c @@ -37,17 +37,6 @@ void tlbiall_el3(void) __asm__ __volatile__("tlbi alle3\n\t" : : : "memory"); } -void tlbiall_current(void) -{ - uint32_t el = get_current_el(); - tlbiall(el); -} - -void tlbiall(uint32_t el) -{ - SWITCH_CASE_TLBI(tlbiall, el); -} - /* TLBIALLIS */ void tlbiallis_el1(void) { @@ -64,17 +53,6 @@ void tlbiallis_el3(void) __asm__ __volatile__("tlbi alle3is\n\t" : : : "memory"); } -void tlbiallis_current(void) -{ - uint32_t el = get_current_el(); - tlbiallis(el); -} - -void tlbiallis(uint32_t el) -{ - SWITCH_CASE_TLBI(tlbiallis, el); -} - /* TLBIVAA */ void tlbivaa_el1(uint64_t va) { |