diff options
| author | Julius Werner <jwerner@chromium.org> | 2015-10-16 13:10:02 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2015-11-17 21:31:20 +0100 |
| commit | 7dcf9d51e5ffadfcf8b5fceddcddb4e1d0a7db37 (patch) | |
| tree | 2860976349922ae1ba54c9a668949c55598469ba /src/arch/arm64/armv8/cpu.S | |
| parent | d3634c108d63d07ce004a66e3abb05e8da57d65b (diff) | |
arm64: tegra132: tegra210: Remove old arm64/stage_entry.S
This patch removes the old arm64/stage_entry.S code that was too
specific to the Tegra SoC boot flow, and replaces it with code that
hides the peculiarities of switching to a different CPU/arch in ramstage
in the Tegra SoC directories.
BRANCH=None
BUG=None
TEST=Built Ryu and Smaug. !!!UNTESTED!!!
Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12078
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/arm64/armv8/cpu.S')
| -rw-r--r-- | src/arch/arm64/armv8/cpu.S | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/src/arch/arm64/armv8/cpu.S b/src/arch/arm64/armv8/cpu.S index 4713ca59f9..711c338685 100644 --- a/src/arch/arm64/armv8/cpu.S +++ b/src/arch/arm64/armv8/cpu.S @@ -21,7 +21,8 @@ * Bring an ARMv8 processor we just gained control of (e.g. from IROM) into a * known state regarding caches/SCTLR/PSTATE. Completely cleans and invalidates * icache/dcache, disables MMU and dcache (if active), and enables unaligned - * accesses, icache and branch prediction (if inactive). Clobbers R22 and R23. + * accesses, icache and branch prediction (if inactive). Seeds the stack and + * initializes SP_EL0. Clobbers R22 and R23. */ ENTRY(arm64_init_cpu) /* Initialize PSTATE (unmask all exceptions, select SP_EL0). */ @@ -60,5 +61,17 @@ ENTRY(arm64_init_cpu) dsb sy isb + /* Initialize stack with sentinel value to later check overflow. */ + ldr x2, =0xdeadbeefdeadbeef + ldr x0, =_stack + ldr x1, =_estack +1: + stp x2, x2, [x0], #16 + cmp x0, x1 + bne 1b + + /* Leave a line of beef dead for easier visibility in stack dumps. */ + sub sp, x0, #16 + ret x23 ENDPROC(arm64_init_cpu) |