diff options
| author | Furquan Shaikh <furquan@google.com> | 2014-06-11 14:48:37 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-02-25 20:01:44 +0100 |
| commit | 26a8747ccaa1bf799cfb03c8ccaaf4205196f108 (patch) | |
| tree | eaef5106fe8ffff05a54b81602e1fdcb65195770 /src/arch/arm64/armv8/cache.c | |
| parent | 595a40cfc92baecca9c58a7a95ae38ce72582f39 (diff) | |
coreboot arm64: Add library for system access
Add support for library functions required to access different system registers:
1) PSTATE and special purpose registers
2) System control registers
3) Cache-related registers
4) TLB maintenance registers
5) Misc barrier related functions
BUG=None
BRANCH=None
TEST=Compiles successfully
Original-Change-Id: I8809ca2b67b8e560b34577cda1483ee009a1d71a
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203490
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 5da840c5d1f3d8fdf8cc0d7c44772bf0cef03fbb)
armv8: GPL license armv8 lib
BUG=None
BRANCH=None
TEST=Compiles successfully.
Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250950
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e)
Get the library and the GPL license in a single commit.
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I4753a6b0d13a6f7515243bfa8e749e250fdd749d
Reviewed-on: http://review.coreboot.org/8465
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/arch/arm64/armv8/cache.c')
| -rw-r--r-- | src/arch/arm64/armv8/cache.c | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index a0eff46e20..918a883303 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -34,13 +34,14 @@ #include <stdint.h> #include <arch/cache.h> +#include <arch/lib_helpers.h> void tlb_invalidate_all(void) { /* TLBIALL includes dTLB and iTLB on systems that have them. */ - tlbiall(current_el()); - dsb(); - isb(); + tlbiall_current(); + dsb(); + isb(); } unsigned int dcache_line_bytes(void) @@ -51,7 +52,7 @@ unsigned int dcache_line_bytes(void) if (line_bytes) return line_bytes; - ccsidr = read_ccsidr(); + ccsidr = raw_read_ccsidr_el1(); /* [2:0] - Indicates (Log2(number of words in cache line)) - 4 */ line_bytes = 1 << ((ccsidr & 0x7) + 4); /* words per line */ line_bytes *= sizeof(uint32_t); /* bytes per word */ @@ -125,18 +126,18 @@ void dcache_mmu_disable(void) uint32_t sctlr; flush_dcache_all(); - sctlr = read_sctlr(current_el()); + sctlr = raw_read_sctlr_current(); sctlr &= ~(SCTLR_C | SCTLR_M); - write_sctlr(sctlr, current_el()); + raw_write_sctlr_current(sctlr); } void dcache_mmu_enable(void) { uint32_t sctlr; - sctlr = read_sctlr(current_el()); + sctlr = raw_read_sctlr_current(); sctlr |= SCTLR_C | SCTLR_M; - write_sctlr(sctlr, current_el()); + raw_write_sctlr_current(sctlr); } void cache_sync_instructions(void) |