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| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-05 17:29:12 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-10 19:01:22 +0000 |
| commit | 5461662c6626898947aca193011761c9530c71d0 (patch) | |
| tree | 39525836cb27c53d19fcc868f166eb40ed742051 /src/arch/arm/libgcc/ashldi3.S | |
| parent | 466edb51b4b0c19486f14f43bee8d6834c52abc9 (diff) | |
soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI
Required so we pass SPI information down to depthcharge.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/arch/arm/libgcc/ashldi3.S')
0 files changed, 0 insertions, 0 deletions