diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2014-02-27 14:56:39 -0800 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-12-17 04:53:05 +0100 |
| commit | f574a327eed82ce00ea94d3f904f3dd8001d240c (patch) | |
| tree | 61083257eb1013a8043a6569e483316b44e6f1f1 /src/arch/arm/include | |
| parent | 032c84381751bab0fe1da2e963af41cbe52c303d (diff) | |
ARM: Use LPAE for Virtual Address Translation
This change introduces LPAE for virtual address translation. To enable it, set
ARM_LPAE. Boot slows down about 4ms on Tegra124 with LPAE enabled.
TEST=Booted nyan with and without LPAE. Built nyan_big and daisy.
BUG=None
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@google.com>
Original-Change-Id: I74aa729b6fe6d243f57123dc792302359c661cad
Original-Reviewed-on: https://chromium-review.googlesource.com/187862
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 6d8c8b2bbdc70555076081eb3bfaabde7b4a398f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8980375c14758af35f7d5ec5244be963e5462d8a
Reviewed-on: http://review.coreboot.org/7749
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch/arm/include')
| -rw-r--r-- | src/arch/arm/include/armv7/arch/cache.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index 470eb55108..dde2c08c1d 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -111,10 +111,34 @@ static inline void write_dacr(uint32_t val) asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (val)); } +/* read memory model feature register 0 (MMFR0) */ +static inline uint32_t read_mmfr0(void) +{ + uint32_t mmfr; + asm volatile ("mrc p15, 0, %0, c0, c1, 4" : "=r" (mmfr)); + return mmfr; +} +/* read MAIR0 (memory address indirection register 0) */ +static inline uint32_t read_mair0(void) +{ + uint32_t mair; + asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r" (mair)); + return mair; +} +/* write MAIR0 (memory address indirection register 0) */ +static inline void write_mair0(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r" (val)); +} /* write translation table base register 0 (TTBR0) */ static inline void write_ttbr0(uint32_t val) { +#if CONFIG_ARM_LPAE + asm volatile ("mcrr p15, 0, %[val], %[zero], c2" : : + [val] "r" (val), [zero] "r" (0)); +#else asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory"); +#endif } /* read translation table base control register (TTBCR) */ |