ARM: Generalize armv7 as arm.

There are ARM systems which are essentially heterogeneous multicores where
some cores implement a different ARM architecture version than other cores. A
specific example is the tegra124 which boots on an ARMv4 coprocessor while
most code, including most of the firmware, runs on the main ARMv7 core. To
support SOCs like this, the plan is to generalize the ARM architecture so that
all versions are available, and an SOC/CPU can then select what architecture
variant should be used for each component of the firmware; bootblock,
romstage, and ramstage.

Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171338
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>

ARM: Split out ARMv7 code and make it possible to have other arch versions.

We don't always want to use ARMv7 code when building for ARM, so we should
separate out the ARMv7 code so it can be excluded, and also make it possible
to include code for some other version of the architecture instead, all per
build component for cases where we need more than one architecture version
at a time.

The tegra124 bootblock will ultimately need to be ARMv4, but until we have
some ARMv4 code to switch over to we can leave it set to ARMv7.

Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7
Reviewed-on: https://chromium-review.googlesource.com/171400
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483)

Squashed two related patches for splitting ARM support into general
ARM support and ARMv7 specific pieces.

Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6782
Tested-by: build bot (Jenkins)

1 files changed, 144 insertions, 0 deletions

diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
new file mode 100644
index 0000000000..cc915a6a33
--- /dev/null
+++ b/src/arch/arm/armv7/mmu.c
@@ -0,0 +1,144 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <config.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#include <cbmem.h>
+#include <console/console.h>
+
+#include <arch/cache.h>
+#include <arch/io.h>
+
+static void *const ttb_buff = (void *)CONFIG_TTB_BUFFER;
+
+void mmu_disable_range(unsigned long start_mb, unsigned long size_mb)
+{
+	unsigned int i;
+	uint32_t *ttb_entry = ttb_buff;
+	printk(BIOS_DEBUG, "Disabling: 0x%08lx:0x%08lx\n",
+			start_mb*MiB, start_mb*MiB + size_mb*MiB - 1);
+
+	for (i = start_mb; i < start_mb + size_mb; i++)
+		writel(0, &ttb_entry[i]);
+
+	for (i = start_mb; i < start_mb + size_mb; i++) {
+		dccmvac((uintptr_t)&ttb_entry[i]);
+		tlbimvaa(i*MiB);
+	}
+}
+
+void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
+		enum dcache_policy policy)
+{
+	unsigned int i;
+	uint32_t attr;
+	uint32_t *ttb_entry = ttb_buff;
+	const char *str = NULL;
+
+	/*
+	 * Section entry bits:
+	 * 31:20 - section base address
+	 *    18 - 0 to indicate normal section (versus supersection)
+	 *    17 - nG, 0 to indicate page is global
+	 *    16 - S, 0 for non-shareable (?)
+	 *    15 - APX, 0 for full access
+	 * 14:12 - TEX, 0b000 for outer and inner write-back
+	 * 11:10 - AP, 0b11 for full access
+	 *     9 - P, ? (FIXME: not described or possibly obsolete?)
+	 *  8: 5 - Domain
+	 *     4 - XN, 1 to set execute-never (and also avoid prefetches)
+	 *     3 - C, 1 for cacheable
+	 *     2 - B, 1 for bufferable
+	 *  1: 0 - 0b10 to indicate section entry
+	 */
+
+	switch(policy) {
+	case DCACHE_OFF:
+		/* XN set to avoid prefetches to uncached/unbuffered regions */
+		attr = (0x3 << 10) | (1 << 4) | 0x2;
+		str = "off";
+		break;
+	case DCACHE_WRITEBACK:
+		attr =  (0x3 << 10) | (1 << 3) | (1 << 2) | 0x2;
+		str = "writeback";
+		break;
+	case DCACHE_WRITETHROUGH:
+		attr =  (0x3 << 10) | (1 << 3) | 0x2;
+		str = "writethrough";
+		break;
+	default:
+		printk(BIOS_ERR, "unknown dcache policy: %02x\n", policy);
+		return;
+	}
+
+	printk(BIOS_DEBUG, "Setting dcache policy: 0x%08lx:0x%08lx [%s]\n",
+			start_mb << 20, ((start_mb + size_mb) << 20) - 1, str);
+
+	/* Write out page table entries. */
+	for (i = start_mb; i < start_mb + size_mb; i++)
+		writel((i << 20) | attr, &ttb_entry[i]);
+
+	/* Flush the page table entries, and old translations from the TLB. */
+	for (i = start_mb; i < start_mb + size_mb; i++) {
+		dccmvac((uintptr_t)&ttb_entry[i]);
+		tlbimvaa(i*MiB);
+	}
+}
+
+void mmu_init(void)
+{
+	/*
+	 * For coreboot's purposes, we will create a simple L1 page table
+	 * in RAM with 1MB section translation entries over the 4GB address
+	 * space.
+	 * (ref: section 10.2 and example 15-4 in Cortex-A series
+	 * programmer's guide)
+         */
+	printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff);
+
+	/*
+	 * Disable TTBR1 by setting TTBCR.N to 0b000, which means the TTBR0
+	 * table size is 16KB and has indices VA[31:20].
+	 *
+	 * ref: Arch Ref. Manual for ARMv7-A, B3.5.4,
+	 */
+	write_ttbcr(read_ttbcr() & ~0x3);
+
+	/*
+	 * Translation table base 0 address is in bits 31:14-N, where N is given
+	 * by bits 2:0 in TTBCR (which we set to 0). All lower bits in this
+	 * register should be zero for coreboot.
+	 */
+	write_ttbr0((uintptr_t)ttb_buff);
+
+	/* disable domain-level checking of permissions */
+	write_dacr(~0);
+}