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authorShaunak Saha <shaunak.saha@intel.com>2016-08-02 17:25:13 -0700
committerAaron Durbin <adurbin@chromium.org>2016-08-04 16:14:14 +0200
commit60b4618a841a2aecd5a9a37bd451f1e6af7e6b1a (patch)
tree30d149cbdb81a26d94ec0571acd26da77231c1e6 /src/acpi
parentb6739d1b5666267a1c536bf8635e174436b836ae (diff)
soc/apollolake: Return correct wake status in _SWS
Wake status is calculated from the four pairs of gpe0 in cbmem CBMEM_ID_POWER_STATE which is filled very early in romstage and depends on the routing information in PMC GPE_CFG register. Coreboot sets the proper value of routing based on devicetree from pmc_init. But when system goes to S3 on waking up PMC is writing default values again in GPE_CFG which results in returning wrong wake status in _SWS. This patch corrects that behaviour by correcting the gpe0 pairs in cbmem after PMC sets the routing table in resume path. BUG=chrome-os-partner:54876 TEST=On resume through powerbtn, lidopen, keyboard press, etc. we are getting proper wake status. Change-Id: I5942d5c20d8c6aef73468dc611190bb7c49c7c7a Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16040 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
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