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| author | Subrata Banik <subratabanik@google.com> | 2023-04-06 18:48:03 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-04-11 11:38:43 +0000 |
| commit | c484c1a9f6929f2720ec300b134ffb1c817d8683 (patch) | |
| tree | 4549d53e7560f22d023d3eda0448b45411a276f1 /src/acpi/acpigen_pci.c | |
| parent | 9629f94c4e7acd50a198cdec90418e3a2405127c (diff) | |
mb/intel/mtlrvp: Update Flash Layout to fit WP_RO within 4MB
This patch updates the MTLRVP flash layout to optimize WP_RO to 4MB.
Changes for chromeos.fmd:
SI_BIOS:
RW_SECTION_A/B: Reduce to 7MB.
RW_LEGACY: Reduce to 1MB.
RW_MISC: Increased to 1MB.
RW_UNUSED: 3MB (reserved)
WP_RO: Reduce to 4MB
Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the
SPI Flash.
BUG=b:277143384
TEST=Able to build and boot intel/mtlrvp with FSP release and debug image.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibd1ea7a3a2cd21928b8e33473c7bdddfad17c636
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/acpi/acpigen_pci.c')
0 files changed, 0 insertions, 0 deletions