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authorReka Norman <rekanorman@google.com>2022-12-19 11:11:48 +1100
committerSubrata Banik <subratabanik@google.com>2023-01-06 10:39:35 +0000
commit166c30309e99aa04aeb46658527b3e20899a451c (patch)
tree267fc0db3e3d0655aec96fffde2710ee77d94b3e /src/Kconfig
parent17c847b5eab2ae5bbe709b7cfb7c02f6fa0395e5 (diff)
Kconfig: Allow mainboards to disable stage cache
On recent Intel ChromeOS devices, although S3 is still supported, only S0ix is used on user devices, so we don't care about optimising S3 resume time. Disabing the stage cache saves boot time at the cost of increasing the S3 resume time. E.g. on nissa this reduces boot time by 6 ms and increases S3 resume time by 89 ms. BUG=b:247940538, b:192032803 TEST=Build and boot on nissa with MAINBOARD_DISABLE_STAGE_CACHE selected. Change-Id: I243a401a112a12bb824c5447a8fecc99500f7739 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/Kconfig')
-rw-r--r--src/Kconfig9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/Kconfig b/src/Kconfig
index f16b53c47d..f68553c2a0 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -347,7 +347,7 @@ endif
choice
prompt "Stage Cache for ACPI S3 resume"
- default NO_STAGE_CACHE if !HAVE_ACPI_RESUME
+ default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || MAINBOARD_DISABLE_STAGE_CACHE
default TSEG_STAGE_CACHE if SMM_TSEG
config NO_STAGE_CACHE
@@ -380,6 +380,13 @@ config CBMEM_STAGE_CACHE
endchoice
+config MAINBOARD_DISABLE_STAGE_CACHE
+ bool
+ help
+ Selected by mainboards which wish to disable the stage cache.
+ E.g. mainboards which don't use S3 resume in the field may wish to
+ disable it to save boot time at the cost of increasing S3 resume time.
+
config UPDATE_IMAGE
bool "Update existing coreboot.rom image"
help