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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-18 00:19:06 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-19 19:30:40 +0000
commit6766f4fd046604e6376c9769cd5f8357dec6a80a (patch)
treed373064f4d454c9c8a4be15421df8504e55b0dbc /src/Kconfig
parent23c1c4e153e8f1311b2e04a19a7e0c66d648e972 (diff)
arch/x86: Fix S3 resume without stage cache
It was possible to have NO_STAGE_CACHE=n and at the same time have TSEG_STAGE_CACHE=n and CBMEM_STAGE_CACHE=n. This resulted with a failing attempt to load STAGE_POSTCAR from the stage cache, but not loading it from CBFS either. Make it a three-way choice between different STAGE_CACHE options. For AGESA disable CBMEM_STAGE_CACHE by default, as it is no longer needed to have functional ACPI S3 resume and it is not allowed se use keyword select for symbols inside choice blocks. Change-Id: I0da3e1cf4c92817ffabbb02eda3476ecdfdfa278 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37683 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/Kconfig')
-rw-r--r--src/Kconfig29
1 files changed, 17 insertions, 12 deletions
diff --git a/src/Kconfig b/src/Kconfig
index 25bb450174..b78b162e9d 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -274,18 +274,28 @@ config RELOCATABLE_RAMSTAGE
wake. When selecting this option the romstage is responsible for
determing a stack location to use for loading the ramstage.
+choice
+ prompt "Stage Cache for ACPI S3 resume"
+ default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE
+ default TSEG_STAGE_CACHE if SMM_TSEG
+
+config NO_STAGE_CACHE
+ bool "Disabled"
+ help
+ Do not save any component in stage cache for resume path. On resume,
+ all components would be read back from CBFS again.
+
config TSEG_STAGE_CACHE
- bool
- default y
- depends on !NO_STAGE_CACHE && SMM_TSEG
+ bool "TSEG"
+ depends on SMM_TSEG
help
The option enables stage cache support for platform. Platform
can stash copies of postcar, ramstage and raw runtime data
inside SMM TSEG, to be restored on S3 resume path.
config CBMEM_STAGE_CACHE
- bool "Cache stages in CBMEM"
- depends on !NO_STAGE_CACHE && !TSEG_STAGE_CACHE
+ bool "CBMEM"
+ depends on !SMM_TSEG
help
The option enables stage cache support for platform. Platform
can stash copies of postcar, ramstage and raw runtime data
@@ -297,6 +307,8 @@ config CBMEM_STAGE_CACHE
If unsure, select 'N'
+endchoice
+
config UPDATE_IMAGE
bool "Update existing coreboot.rom image"
help
@@ -1153,13 +1165,6 @@ config RELOCATABLE_MODULES
building relocatable modules in the RAM stage. Those modules can be
loaded anywhere and all the relocations are handled automatically.
-config NO_STAGE_CACHE
- bool
- default y if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE
- help
- Do not save any component in stage cache for resume path. On resume,
- all components would be read back from CBFS again.
-
config GENERIC_GPIO_LIB
bool
help