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author | Felix Held <felix-coreboot@felixheld.de> | 2023-05-31 16:21:35 +0200 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 00:19:58 +0000 |
commit | a4f4b0a922e01a7cacced10e55b82e485b9b4aaf (patch) | |
tree | c38bd4d113b60de22bab2ef1a5a2b3d5cd667187 /spd/lp5 | |
parent | 9adc33d0d080f11db33ecc7fb25be93c8507c36f (diff) |
soc/amd/mendocino/chip: use common data fabric domain resource code
Use the new common AMD code that gets the usable non-fixed MMIO windows
from the data fabric MMIO decode registers and generate the PCI0 _CRS
ACPI code based on those regions. For a more detailed description see
the corresponding patch that changes the Picasso code to use this new
code. In contrast to the Picasso code, this change will drop the
unneeded _STA method inside the PCI0 scope which wasn't present in
Picasso's ACPI code before it got replaced by the SSDT that gets
generated by amd_pci_domain_fill_ssdt.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iad34d74d9f6cbed1d8a71a561a505f563e31db18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'spd/lp5')
0 files changed, 0 insertions, 0 deletions