diff options
| author | Frank Wu <frank_wu@compal.corp-partner.google.com> | 2022-12-14 10:03:50 +0800 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2022-12-15 14:28:02 +0000 |
| commit | 3a4e201a21551acae101a5b87e771b01421dc785 (patch) | |
| tree | 8328fc28c72c50e6155dd7bc9453cdcd97e3d9ff /spd/lp5/set-0 | |
| parent | 315d3264b603e16f5694ac0b61b139f18409e51e (diff) | |
spd/lp5: Update memory configuration of H9JCNNNFA5MLYR-N6E
Update bitWidthPerChannel in memory_parts.json and re-generate the SPD.
Then the device boots successfully with DDR H9JCNNNFA5MLYR-N6E.
BUG=b:261530632
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: Ib78c2e28394206b59c41b6b28cf24d8a756f7ae9
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'spd/lp5/set-0')
| -rw-r--r-- | spd/lp5/set-0/parts_spd_manifest.generated.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt index 10f6c1bc96..3b7f301ff6 100644 --- a/spd/lp5/set-0/parts_spd_manifest.generated.txt +++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt @@ -16,6 +16,6 @@ MT62F1G32D2DS-026 WT:B,spd-7.hex MT62F2G32D4DS-026 WT:B,spd-8.hex K3KL8L80CM-MGCT,spd-7.hex K3KL9L90CM-MGCT,spd-8.hex -H9JCNNNFA5MLYR-N6E,spd-9.hex H58G66BK7BX067,spd-8.hex H58G56BK7BX068,spd-7.hex +H9JCNNNFA5MLYR-N6E,spd-4.hex |