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| author | Petr Cvek <petrcvekcz@gmail.com> | 2022-06-16 17:13:22 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-14 12:51:12 +0000 |
| commit | e75bb01efa59812776b15266ef26b35c993b903b (patch) | |
| tree | 10f0cf78bc8586d1efd4800385e200e51ac72a66 /spd/lp5/set-0 | |
| parent | f87489bbae5bb1ae3b17b6a03af9e309769b1f72 (diff) | |
northbridge/intel/i945: Fix GCC optimizing out cache preload jump
Clock config setup must be run from cache. Original code used "goto"
to prefetch the code required to update the VCO (by jumping after
the code and back before). The GCC since at least 12.1.0 and clang
since at least 13.0.1 will elimitate these jumps.
Use inline assembler to force the original code flow.
TEST=Verified assembly code is the same as generated by GCC 12.1.0
and boot tested on Kontron 986LCD-M.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: I67c2072b5983a5bd845631af136ae5a003c7ea3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'spd/lp5/set-0')
0 files changed, 0 insertions, 0 deletions