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authorFelix Held <felix-coreboot@felixheld.de>2023-12-21 00:23:35 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-12-28 16:54:51 +0000
commit580c166eb27a4780ece5e36f7e08e08ada217e7b (patch)
tree7e9102a71d18b3ba4f2179ba2ddef81d316707ba /spd/lp5/memory_parts.json
parent8d8c68157dd1f3bb6db021b0031b79b28e7c29aa (diff)
mb/pcengines/apu2/mainboard: add/fix comments on PIRQ table
Align the comments on the PIRQ table entries for the PCI bridge devices to the external PCIe ports with the devicetrees of the different APU boards. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id25ae8422c7c5c79dc8666a28a8219c77af324da Reviewed-on: https://review.coreboot.org/c/coreboot/+/79676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'spd/lp5/memory_parts.json')
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