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authorRobert Zieba <robertzieba@google.com>2022-10-03 14:50:55 -0600
committerFelix Held <felix-coreboot@felixheld.de>2022-10-26 22:02:32 +0000
commitb3b27f7dea3ac7170adfbfc7e6d4ca7bde9ab780 (patch)
tree0e1c20fd075b638563f4569ca984a048c34c08b6 /spd/lp5/memory_parts.json
parent956432cbb7f0a5a1618fb1111158cf3a8ede5f60 (diff)
soc/amd/mendocino: Enable GPP clk req disabling for disabled devices
Enable GPP clk req disabling for disabled PCIe devices. If a clk req line is enabled for a PCIe device that is not actually present and enabled then the L1SS could get confused and cause issues with suspending the SoC. BUG=b:250009974 TEST=Ran on skyrim proto device, verified that clk reqs are set appropriately Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68139 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'spd/lp5/memory_parts.json')
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